<DaKnig>
I have no idea, I have been messing with it for a few hours now
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<DaKnig>
it's like VGA_testbench.py doesnt use the Controller from top_level.py for some reason
<DaKnig>
changing the second file does nothing
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<d1b2>
<dub_dub_11> for nmigen-boards: what would be the best way of allowing the user to specify a reset button/pin?
<d1b2>
<dub_dub_11> afaict the DE1-soc board doesn't have a dedicated FPGA reset button (only HPS resets)
<d1b2>
<dub_dub_11> would I put something like python default_clk = "fpga_reset_n" then not specify a resource with that name (leaving it up to the user to define one, or would that break things
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<DaKnig>
if there is no reset button, wouldnt it be better just not to define one?
<DaKnig>
if the user wants a custom domain to use some wire as its reset they can do this
<d1b2>
<dub_dub_11> that sounds reasonable
<d1b2>
<dub_dub_11> though with how it works, is it correct that that button would still be unavailable for GPIO even if you never use sync
<d1b2>
<dub_dub_11> ...maybe not, as you would never request it
<d1b2>
<dub_dub_11> it would have to be a seperate Resource though
<d1b2>
<dub_dub_11> so the DE1-SoC has 4 push buttons, say I defined button 3 to be reset but wanted it still usable
<d1b2>
<dub_dub_11> I would need two PinResources
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<DaKnig>
I dont think I understand how this setup works
<DaKnig>
is this pin configurable only as reset?
<DaKnig>
or is it connected to resetting the HPS only?
<DaKnig>
wdym define button 3 to be reset but still have it usable
<Lofty>
dub_dub_11: the reset is invisible to the FPGA, so therefore the FPGA does not have a reset pin bound
<d1b2>
<dub_dub_11> there are two HPS resets yeahbut as Lofty says the FPGA doesn't see them
<d1b2>
<dub_dub_11> other than that, there are 4 user buttons
<Lofty>
dub_dub_11: I helped research for the vendor.intel backend
<Lofty>
And wrote the DE10-Nano/DE0-CV board definitions
<DaKnig>
if it's invisible there's no point in mentioning this in the board file
<Lofty>
^
<d1b2>
<dub_dub_11> oo awesome (ty very much btw, it's so nice not using quartus gui)
<DaKnig>
true!
<DaKnig>
in my case it's vivado, but it's still disgusting :)
<Lofty>
dub_dub_11: if you're really brave, I maintain the Intel Cyclone V frontend for Yosys
<d1b2>
<dub_dub_11> yes, but I'm thinking there should still be a way for the user to reset the fpga design with a button
<DaKnig>
if the user wants to use a button they can do this
<DaKnig>
check out the clock domain part of teh language tutorial
<d1b2>
<dub_dub_11> (Cyclone V is for labs, at home I have a Stratix IV)
<Lofty>
I think the general principle of nMigen is "when in doubt, err towards the side of more user control"
<d1b2>
<dub_dub_11> that's fair
<DaKnig>
you can define a clock domain and override its clock signal/reset signal
<DaKnig>
to use a custom signal
<DaKnig>
... I think you see where this is going
<d1b2>
<dub_dub_11> yeah
<d1b2>
<dub_dub_11> so the user would request a ButtonResource, define one for the reset, request a clock50 resource
<Lofty>
e.g. there was a pull request to nmigen to define a Symbiflow Xilinx backend platform, and we asked them to instead modify the present Vivado Xilinx backend so the user could decide what toolchain to use
<d1b2>
<dub_dub_11> ah cause all the board platforms inherit from the those platforms tight
<Lofty>
Yep
<d1b2>
<dub_dub_11> well, I can't actually find out how one would define your own domain in the language guide 😅 but I am content that I don't need to define a default_reset in the board definition
<d1b2>
<dub_dub_11> ...all I need now then is to wait till I can get in the lab to test it 🙂
<Lofty>
I'm not quite brave enough to submit a PR to use Yosys as an optional frontend
<Lofty>
Well, it technically goes through Yosys anyway, but
<d1b2>
<dub_dub_11> what would yosys as a frontend mean?#
<d1b2>
<dub_dub_11> er I think I am missing something
<Lofty>
Presently, nMigen outputs Yosys' RTLIL, and asks Yosys to convert it to Verilog
<d1b2>
<dub_dub_11> ah right, but Yosys could actually do the synth from RTLIL direct to a netlist of primitives?
<Lofty>
With something fully-open like ECP5, nMigen outputs RTLIL and then Yosys synthesises it all the way to LUTs and flops
<Lofty>
Yes
<d1b2>
<dub_dub_11> and atm Yosys can also do that for some vendor parts (like Cyclone V)?
<d1b2>
<dub_dub_11> or is that still WIP
<d1b2>
<dub_dub_11> .,,I suppose it is always WIP
<Lofty>
Unfortunately, Quartus has Problems that make it a pain to target
<Lofty>
I'd consider it beta quality
<d1b2>
<dub_dub_11> right...
<Lofty>
The biggest stumbling block is initialising RAMs
<d1b2>
<dub_dub_11> ah
<Lofty>
TL;DR Quartus is the only compiler I've ever come across that does not support inline initialisation of memories
<Lofty>
That is, putting the init data in a cell parameter
<d1b2>
<dub_dub_11> from setting it up, it seems like nmigen is calling: quartus_synth, quartus_map, quartus_asm, quartus_sta, quartus_pgm
<d1b2>
<dub_dub_11> and yosys is aiming to replace quartus_syn?
<Lofty>
map/fit/asm/sta/pgm
<d1b2>
<dub_dub_11> ah map fit
<d1b2>
<dub_dub_11> so yosys would do map, fit?
<Lofty>
It would replace map. Kinda.
<d1b2>
<dub_dub_11> hmm
<d1b2>
<dub_dub_11> so project trellis is basically fit/asm/sta?
<d1b2>
<dub_dub_11> (I'm sure this is a simplified overview)
<Lofty>
Because ~Quartus~ even if Yosys synthesises it, you still have to call map to get Quartus to convert it to its internal databases
<d1b2>
<dub_dub_11> oh no
<Lofty>
nextpnr is fit/sta, and Trellis is asm
<Lofty>
For what it's worth, the magic word for an open Cyclone {V,10GX} flow is Project Mistral ;)
<d1b2>
<dub_dub_11> oo fancy
<Lofty>
Symbiflow uses VPR instead for fit/sta, but in the best possible way I wouldn't touch VPR with a barge pole
<d1b2>
<dub_dub_11> 0_0
<Lofty>
That's drifting too off topic though
<d1b2>
<dub_dub_11> yeah probably. thank you for the tips 🙂
<Lofty>
I can't presently help with Stratix IV because I'm too poor to afford a Quartus Standard license
<d1b2>
<dub_dub_11> hopefully covid/government actually allows us to get into labs at some point so I can test the de1
<d1b2>
<dub_dub_11> the de4 which is what I've tested worked really nice though
<d1b2>
<dub_dub_11> (it also uhh... requires a pro licence 😬 )
<Lofty>
But Cyclone V and Cyclone 10 GX are freeware
<Lofty>
And have a lot in common
<Sarayan>
they do?
<Lofty>
From a synthesis point of view
<Lofty>
I'm sure you'll crack the rest of it :P
<Sarayan>
I haven't even dared installing qpro yet :-)
<d1b2>
<dub_dub_11> probably sensible. but I got this board for free from an electronics waste bin so it's my only choice until I have money to spend on an actual devboard
<Lofty>
But Cyclone V support is...relatively mature?
<Lofty>
Relatively by the standards of it being the better part of six months upstream
<awygle>
that's specifically the yosys bit, right?
<Lofty>
Yep
<awygle>
noxtpnr
<Sarayan>
How do you do the support of all the funky things like iobs, fpll, dsp and that kind of fun with yosys btw?
<Lofty>
IOBs are iopadmap
<Lofty>
DSP is dsp2mul and long-term a dedicated Yosys pass
<Lofty>
PLLs are whatever :p
<Sarayan>
any idea how all these will go it nmigen side?
<Sarayan>
s/it/up/
<Lofty>
nMigen likely doesn't care in most instances; they're all just Instances
<d1b2>
<dub_dub_11> and is that currently the only way to use a PLL?
<Lofty>
Instance creates a Verilog cell, yeah
<Lofty>
I think it's something nMigen should provide an abstraction for, but at present it does not
<d1b2>
<dub_dub_11> right
<d1b2>
<dub_dub_11> so it would still be necessary to use quartus clocking wizard at present
<Lofty>
At present
<Lofty>
I intend to provide something along the lines of a megawizard "replacement"
<Lofty>
read: my GUI skills are terrible so it's going to be maybe a CLI command
<d1b2>
<dub_dub_11> that would be nice
<d1b2>
<dub_dub_11> though I think the ideal is import nmigen.pll
<d1b2>
<dub_dub_11> does quartus require the qip file or is the generated verilog file enough
<d1b2>
<dub_dub_11> it seems like generating the verilog wouldn't be too hard
<Lofty>
Neither
<Lofty>
You just instantiate the cell
<Lofty>
qip tells Quartus how to create the verilog file
<Lofty>
But ultimately you can just instantiate the cell and that's enough
<d1b2>
<dub_dub_11> oh right
<d1b2>
<dub_dub_11> huh
<d1b2>
<dub_dub_11> atm though, the verilog file with Instance() can be used to make use of PLLs without otherwise confusing nmigen/yosys?
<Lofty>
Yeah
<d1b2>
<dub_dub_11> cool
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<whitequark>
you don't necessarily have to use the megawizard, you can instantiate the same primitive quartus does in the results of that GUI tool
<whitequark>
it's harder than to use the megawizard, of course, and you can blame Altera for their choice of writing a proprietary GUI instead of properly documenting the primitive
<whitequark>
though basically every other vendor does this as well, Altera really went all-in on crappy GUI tools
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<DaKnig>
the issue I had yesterday turned out to be a problem with my editor. for some reason it does not recompile the file if I re-run it.
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<d1b2>
<dub_dub_11> well if there's vendor specific work to be done I'd gladly contribute to supporting the altpll in nmigen more easily
<whitequark>
there's an issue about PLLs on the tracker