<whitequark>
mwk: okay, so the plan to fix this problem before was to do it at the same time as getting rid of explicit `yield` in favor of `await` for a few reasons
<whitequark>
that plan is a bit complicated though and there was no progress on it so far
<mwk>
right
<whitequark>
what i'm thinking is that we can add a new function, `add_bench_process`, which implicitly calls `yield Settle()` after ~every other statement
<whitequark>
this is what the new async/await based system would do anyway, just... without async/await
<mwk>
hmm
<mwk>
like for x in process: yield x; yield Settle()?
<whitequark>
more or less
<mwk>
right
<mwk>
there is no way to yield a "composite" command, right?
<mwk>
like make the "default" yield value Tick() + Settle()
<whitequark>
that won't be enough
<whitequark>
think of what happens if you observe combinatorial feedback in a testbench
<mwk>
ah, right
<whitequark>
there are two options
<whitequark>
settle after `yield eq()` and settle before `yield sig`
<whitequark>
the latter is perhaps a bit more efficient (you can settle lazily) but it leads to observable races
<whitequark>
if you use multiple bench processes
<whitequark>
whcih is an obscure but valid use case
<mwk>
you'd also need to settle after a Tick
<whitequark>
yeah
<mwk>
in the first case
<whitequark>
and after Delay
<whitequark>
in practice I think just settling after every command is fine at first
<whitequark>
then we can optimize that if necessary
<mwk>
right
<whitequark>
anyway if you're happy with that i can implement it
<mwk>
yeah it sounds good
<whitequark>
mkay
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<_whitenotifier-f>
[nmigen/nmigen] whitequark pushed 1 commit to sim-bench-processes [+0/-0/±2] https://git.io/JTBrQ
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<whitequark>
hm, really?
<mwk>
but anyway, not sure if it's really a big problem
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<whitequark>
so, that's kinda why i put it in a branch and asked you to look at it: i think once you start debugging real VCD traces it becomes apparent
<mwk>
hm, maybe
<mwk>
I mean it's really no different from a module's inputs synchronously changed by its parent module
<whitequark>
it's different, isn't it?
<mwk>
it all happens on the exact same timestamp in the vcd
<mwk>
IMO testbench is kind of the parent module to the DUT
<whitequark>
if a parent module changes inputs, it happens "simultaneously" with the tick, but if a bench changes inputs, it happens "after" the tick because of the implicit settle
<mwk>
if a parent module changes inputs according to combinatorial function of module's outputs, it still happens on a tick
<whitequark>
mhm
<mwk>
testbench reacting to results of the tick within same cycle would be really the same case, no?
<whitequark>
yes, i see your point
<whitequark>
do you mind if we keep it in a branch until the next meeting?
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<mwk>
fine with me
<mwk>
I mean, I'll have to go with git anyway since there's not going to be a release in the next few hours, so I'll just point to my fork I guess
<whitequark>
yeah, I wasn't sure what your plan was exactly
<mwk>
well original plan was to use nmigen release, but this seems to be enough of a confusion point to justify going with git
<whitequark>
right
<_whitenotifier-f>
[nmigen] whitequark commented on issue #377: Our recommended way to write testbenches is racy - https://git.io/JTBiB
<mwk>
like... come one, I can bet some student will end up forgetting the Settle and spending a lot of time debugging it, or just having a testbench with a random one-cycle offset in one particular place where the Settle is missing because they didn't bother to think
<whitequark>
yep
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* zignig
solves a layer 0 problem.
<zignig>
after doing a big update, my remote reset stopped working.
<zignig>
little did I know that going into summer meant that my breadboard FTDI bridge had moved.
<zignig>
5 hours of debug and vcds, pull out the 0.1' header wiggle everything and put it back in.
<zignig>
I don't know how to get an asyncfifo so I can hook it up to my boneless bootloader. !!!
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* zignig
stacks the relevant.
<zignig>
!global ping
<zignig>
all nmigen-o-naughts, can WE pls sublimate nmigen-boards into drivers?
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<zignig>
blinky is working on all boards; et al ; MAY WE have a 16 bit CPU pls...
* zignig
should throbular the ine-ex-stepped.
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<whitequark>
i have no idea what you're asking for
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<zignig>
whitequark: I have two luna stream_interfaces, I wish to make two ansyfifos.
* Lofty
wants whatever zignig is on at the moment
<whitequark>
oh, i don't think i can help you with luna. i meant i don't understand what you want from nmigen-boards
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<_whitenotifier-f>
[nmigen] anuejn commented on issue #386: Inverted DiffPairs in connectors - https://git.io/JTRGV
<_whitenotifier-f>
[nmigen] anuejn commented on issue #386: Inverted DiffPairs in connectors - https://git.io/JTRGi
<_whitenotifier-f>
[nmigen] whitequark commented on issue #386: Inverted DiffPairs in connectors - https://git.io/JTRGS
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<_whitenotifier-f>
[nmigen] anuejn opened issue #510: [RFC] Allow DiffPairs and Pins to be inverted individually - https://git.io/JTRnU
<_whitenotifier-f>
[nmigen] anuejn edited issue #510: [RFC] Allow DiffPairs and Pins to be inverted individually - https://git.io/JTRnU
<_whitenotifier-f>
[nmigen] anuejn edited issue #510: [RFC] Allow DiffPairs and Pins to be inverted individually - https://git.io/JTRnU
<_whitenotifier-f>
[nmigen] whitequark commented on issue #510: [RFC] Allow DiffPairs and Pins to be inverted individually - https://git.io/JTRn7
<_whitenotifier-f>
[nmigen] whitequark edited a comment on issue #510: [RFC] Allow DiffPairs and Pins to be inverted individually - https://git.io/JTRn7
<_whitenotifier-f>
[nmigen] whitequark commented on issue #510: [RFC] Allow DiffPairs and Pins to be inverted individually - https://git.io/JTRcv
<_whitenotifier-f>
[nmigen] whitequark edited a comment on issue #510: [RFC] Allow DiffPairs and Pins to be inverted individually - https://git.io/JTRcv
<_whitenotifier-f>
[nmigen] adamgreig commented on issue #510: [RFC] Allow DiffPairs and Pins to be inverted individually - https://git.io/JTRcC
<key2>
ktemkin: hi. did you manage to get Luna to work on ECP5 serdes finally ? ?
<_whitenotifier-f>
[nmigen] whitequark commented on issue #510: [RFC] Allow DiffPairs and Pins to be inverted individually - https://git.io/JTRcD
<_whitenotifier-f>
[nmigen] anuejn commented on issue #510: [RFC] Allow DiffPairs and Pins to be inverted individually - https://git.io/JTRcx
<_whitenotifier-f>
[nmigen] whitequark commented on issue #510: [RFC] Allow DiffPairs and Pins to be inverted individually - https://git.io/JTRCZ
<_whitenotifier-f>
[nmigen] anuejn commented on issue #510: [RFC] Allow DiffPairs and Pins to be inverted individually - https://git.io/JTRC2
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<FL4SHK>
so I've got a question
<FL4SHK>
with `Interface`, can I do a whole assignment?
<FL4SHK>
i.e. `my_interf.eq(my_other_interf)`
<FL4SHK>
that's one thing I'd want to have given that you can't stick an `Array` within a `PackedStruct`
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<awygle>
g'mornin
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