<Lofty>
I'm targeting an iCE40HX8K (because that seems roughly the chip I want)
<Lofty>
And the idea is to do things effectively voice-serially
<Lofty>
Synthesise one voice on one cycle, then the next on the next cycle
<DaKnig>
do you output using pwm+lpf?
<Lofty>
And so given the options of an SB_RAM4K, that gives me 256 voices
<Lofty>
No, it's going to be digital domain
<DaKnig>
:(
<DaKnig>
I am both happy and sad
<DaKnig>
otoh you cant hear the output but otoh lpf+pwm sounds like crap unless you know what you are doing and design the lpf exactly the way it should be etc
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<whitequark>
not sure about pwm but i find that first order sigma delta plus lpf sounds about as bad as my laptop's speakers
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<Lofty>
It adds character /s
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<whitequark>
i mean, why /s ?
<whitequark>
flaws are often most memorable, and i've actually found the flaws in my sigma delta dac pretty okay
<Lofty>
I think the MiSTer's analogue output is basically that
<Lofty>
But nah, I was considering like an I2S DAC or something.
<DaKnig>
whitequark: why delta sigma and not something like pdm?
<cr1901_modern>
delta sigma == pdm I think
<whitequark>
a specific implementation of pdm, i believe, yes
<_whitenotifier-f>
[nmigen] codecov[bot] edited a comment on pull request #512: Fix {r,w}_level in AsyncFIFOBuffered - https://git.io/JTgbd
<Lofty>
Yeah, that's neat
<_whitenotifier-f>
[nmigen] codecov[bot] edited a comment on pull request #512: Fix {r,w}_level in AsyncFIFOBuffered - https://git.io/JTgbd
<_whitenotifier-f>
[nmigen] codecov[bot] edited a comment on pull request #512: Fix {r,w}_level in AsyncFIFOBuffered - https://git.io/JTgbd
<_whitenotifier-f>
[nmigen] codecov[bot] edited a comment on pull request #512: Fix {r,w}_level in AsyncFIFOBuffered - https://git.io/JTgbd
<_whitenotifier-f>
[nmigen] codecov[bot] edited a comment on pull request #512: Fix {r,w}_level in AsyncFIFOBuffered - https://git.io/JTgbd
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<_whitenotifier-f>
[nmigen] anuejn commented on pull request #512: Fix {r,w}_level in AsyncFIFOBuffered - https://git.io/JTwzy
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<cr1901_modern>
whitequark: I'm guessing you know this already/are choosing not to go down this route, just _just in case_: It should be possible to programmatically install libusbk drivers using libwdi directly (which Zadig uses internally). >>
<cr1901_modern>
This would avoid the need for a GUI. I don't have any insight on how to do this beyond "it exists" though.
<whitequark>
cr1901_modern: wrong channel?
<cr1901_modern>
Ehhh I guess. I'll join #glasgow and repost
<Degi>
Hmh, the ECP5 5 Gbit/s SERDES does not seem to work very well at 6 Gbit/s, but 5.5 Gbit/s seems fine
<whitequark>
10% tolerance?
<Degi>
Maybe, though at 5.5 Gbit/s the signal looks worse too, I didn't do any BER testing though
<Degi>
6.5 Gbit/s seems to be the max where its doing anything at all, at 7 Gbit/s the output looks very weird and is low frequency
<Degi>
(Though these measurement were taken with a 350 MHz oscilloscope, so take with some salt)
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<whitequark>
does the PLL even lock at 7 Gbps?
<Degi>
No
<Degi>
At 6.75 it barely does, at 6.5 it seems to somewhat sorta do (it outputs something at that data rate, but the data looks pretty broken)
<whitequark>
wait, don't you have a PLL locked output?