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[nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JTggs
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[nmigen/nmigen] whitequark cbd74c5 - Deploying to gh-pages from @ df70aae887e6e3a06df0044b419eb40674543c18 🚀
<d1b2>
<marble> When simulating, are the .vcd and .gtkw files generated by nmigen or by the icestorm toolchain?
<vup>
I assume you mean when using pysim? Then they are generated by nmigen.
<d1b2>
<marble> Ah. found the corresponding file ^^'. I thought that the sigrok file format would be a nice additional option. This would make the stack decoders available
<vup>
doesn't sigrok already have a vcd import option?
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<d1b2>
<marble> I just tried that and I get no traces
<d1b2>
<marble> The signal names are there, but there seems to be an error with the data. the traces are there when I open the same file in gtkwave
<vup>
however building pulseview against libsigrok from master and opening a vcd file just segfaults...
<whitequark>
marble: this is a pulseview issue, yeah
<whitequark>
i've asked the sigrok folks to do something about it a very long time ago... and ~1y ago it actually worked
<whitequark>
with multibit vcd signals
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<d1b2>
<marble> the three last commits on libsigrok are regarding vcd
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<d1b2>
<marble> worksn't on my machine :/
<anuejn>
when I try to run the nmigen testsuite i get the error "smt2: ERROR: Unsupported cell type $sdff for cell rst_cdc.$auto$opt_dff.cc:702:run$139."
<anuejn>
in FIFOFormalCase
<whitequark>
out of date yosys or sby
<anuejn>
is this some kind of yosys problem
<anuejn>
okay thanks :)
<whitequark>
not and/or. the problem is yosys/sby mismatch specifically
<anuejn>
ok will try to update both
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<anuejn>
that helped, thanks :)
<d1b2>
<EmilJ> Qs like this might be best to ask and answer on stackoverflow or similar
<d1b2>
<EmilJ> So people in the future with a similar problem can help themselves
<d1b2>
<EmilJ> Is there something one has to do to have a "tag" on stackoverflowfor nmigen or is it just a string people type in
<whitequark>
you can add a tag yourself
<whitequark>
or if you don't have enough reputation, i can do that
<d1b2>
<EmilJ> Yeah, I seem to have 70x less reputation than is required
<d1b2>
<EmilJ> I think this could help both usage and development, if it stops being a "read the source or ask around" but more of a "google the error and first thing tells you what to do" deal
<whitequark>
gimme the question
<whitequark>
i have almost 20k reputation so
<d1b2>
<EmilJ> I don't... have a question
<whitequark>
ohh
<whitequark>
sorry, i didn't realize that
<d1b2>
<EmilJ> my point was just "wouldn't offloading implementation details Q&A require less of an immediate reaction than IRC channel showing up activity"
<vup>
its sad, that the irc logs seem to be so hard to find using google, probably because nothing links to them?
<whitequark>
gotcha
<d1b2>
<EmilJ> I haven't really done anything in nmigen, only wired together some code for HDMI out by vup and anuejn
<whitequark>
wtf, the html for the text is there, but cached page doesn't show it
<miek>
huh, the log section ends up too small for some reason? if i go in and increase the height manually the content is there: https://i.imgur.com/lBoSjJy.png
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<whitequark>
ahh, probably a css issue
<whitequark>
i remember being super frustrated with css on that page and asking for help
<whitequark>
maybe it's still not quite good enough
<whitequark>
anyway, it's still indexed, no one looks at cached pages anyway
<vup>
weird
<_whitenotifier-f>
[nmigen] anuejn opened pull request #511: improve spec directory name of FHDLTestCase - https://git.io/JTgdr
<_whitenotifier-f>
[nmigen] whitequark commented on pull request #511: improve spec directory name of FHDLTestCase - https://git.io/JTgd1
<_whitenotifier-f>
[nmigen] whitequark commented on pull request #511: improve spec directory name of FHDLTestCase - https://git.io/JTgdH
<_whitenotifier-f>
[nmigen] codecov[bot] commented on pull request #511: improve spec directory name of FHDLTestCase - https://git.io/JTgdQ
<_whitenotifier-f>
[nmigen] codecov[bot] edited a comment on pull request #511: improve spec directory name of FHDLTestCase - https://git.io/JTgdQ
<_whitenotifier-f>
[nmigen] codecov[bot] edited a comment on pull request #511: improve spec directory name of FHDLTestCase - https://git.io/JTgdQ
<_whitenotifier-f>
[nmigen] whitequark commented on pull request #511: improve spec directory name of FHDLTestCase - https://git.io/JTgFm
<_whitenotifier-f>
[nmigen] anuejn commented on pull request #511: improve spec directory name of FHDLTestCase - https://git.io/JTgFn
<_whitenotifier-f>
[nmigen] anuejn synchronize pull request #511: improve spec directory name of FHDLTestCase - https://git.io/JTgdr
<_whitenotifier-f>
[nmigen] codecov[bot] edited a comment on pull request #511: improve spec directory name of FHDLTestCase - https://git.io/JTgdQ
<_whitenotifier-f>
[nmigen] codecov[bot] edited a comment on pull request #511: improve spec directory name of FHDLTestCase - https://git.io/JTgdQ
<_whitenotifier-f>
[nmigen] codecov[bot] edited a comment on pull request #511: improve spec directory name of FHDLTestCase - https://git.io/JTgdQ
<_whitenotifier-f>
[nmigen] codecov[bot] edited a comment on pull request #511: improve spec directory name of FHDLTestCase - https://git.io/JTgdQ
<_whitenotifier-f>
[nmigen] anuejn opened pull request #512: Fix {r,w}_level in AsyncFIFOBuffered - https://git.io/JTgbP
<awygle>
i definitely did write that. and it is level-related logic, if you check the original "add r,w_level" pr you'll see that produce_r_bin didn't exist before then
<awygle>
i think it wasn't synced to the actual data, being on a one cycle delay, which is why i made the change to comb
<awygle>
btw thanks for fixing this, i kept meaning to get back to it but ... you know how it is