#nmigen on 2020-09-22 — irc logs at freenode.irclog.whitequark.org

2020-09-07 15:44 ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each Monday at 1800 UTC · next meeting September 14th

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00:42 <_whitenotifier-f> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JUzOe

00:42 <_whitenotifier-f> [YoWASP/yosys] whitequark c52003f - Update dependencies.

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05:22 <zignig_> ping!

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08:15 <lkcl> whitequark: nothing immediate / critical. which is good as it's heads-down to meet the end-october 180nm MVP deadline

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08:52 <lkcl> zignig_, pong

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09:20 <sebinho> Hi all, is there a simple way to specify the name of the top level module? By default it is "top", but any way to make it custom? thx

09:31 <jfng> sebinho: platform.build(..., name="foo")

09:31 <jfng> also works with verilog.convert() and friends

09:37 <sebinho> jfng thanks for your reply

09:38 <lkcl> sebinho: https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/issuer_verilog.py;h=8cd713f8d1393ad85f4179e078e44f47c8d4a37f;hb=HEAD#l36https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/issuer_verilog.py;h=8cd713f8d1393ad85f4179e078e44f47c8d4a37f;hb=HEAD#l36

09:38 <lkcl> like that.

09:44 <sebinho> lkcl (y)

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11:04 <zignig_> lkcl: thanks for the pong, I was wondreing how to make a clean reset on __anohter__ Elabortial.

11:05 <zignig_> I have a construct and I am trying to make an isolated reset;

11:06 <zignig_> ... sub reset.

11:07 * zignig_ is ready for sleepy time.

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11:14 <lkcl> aw doh he's gone :)

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14:37 <d1b2> <EmilJ> Looks like I

14:37 <d1b2> <EmilJ> *Looks like I'll be writing nmigen board support for Pynq Z2 as a part of my "computer interfaces" course project

14:38 <d1b2> <EmilJ> Here's the plan if you're curious: https://gitlab.com/tywonemi-school-stuff/zynq-hdmi-nmigen

14:38 <d1b2> <EmilJ> vup: ping

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