ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each Monday at 1800 UTC · next meeting September 14th
<_whitenotifier-f> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JUROE
<_whitenotifier-f> [YoWASP/nextpnr] whitequark f0be080 - Update dependencies.
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<d1b2> <GenTooMan> Documentation would be great.
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<lkcl> mithro: that was hilarious when ilang "just worked" in hdl-diagrams. it shouldn't have been too big a surprise, it's just yosys after all
<lkcl> mithro: i wonder.... i wonder if it would not be considered unreasonable to not need the code to print out an ilang file
<lkcl> instead to have a syntax "hdl-diagram:: code/nmigen/counter.py:Counter
<lkcl> hmmm that wouldn't work because some functions - some classes - take parameters Counter(16)
<lkcl> how about a function that takes no parameters and returns the ilang as a string?
<lkcl> the reason i suggest that is because, often, you might have the file doing something different (or, extra) such as "run a unit test by default"
<lkcl> which, using that technique, would end up with the unit test or other side-effects being executed as part of the documentation!
<Lofty> lkcl: "ILANG" doesn't really exist anymore. It's just a textual form of RTLIL, and the distinction between RTLIL [the IR] and ILANG [the text form of the IR] was confusing. So it's all just RTLIL now.
<lkcl> Lofty: ah thank you for the right acronym :)
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<_whitenotifier-f> [nmigen-boards] whitequark reviewed pull request #111 commit - https://git.io/JURH1
<_whitenotifier-f> [nmigen] whitequark closed issue #496: no doc string for `en` in `ReadPort` - https://git.io/JUC7x
<_whitenotifier-f> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JURQJ
<_whitenotifier-f> [nmigen/nmigen] jfng 69ed491 - hdl.mem: document ReadPort and WritePort.
<_whitenotifier-f> [nmigen] whitequark closed pull request #499: hdl.mem: document ReadPort and WritePort. - https://git.io/JU4Ve
<_whitenotifier-f> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-2/±13] https://git.io/JURQk
<_whitenotifier-f> [nmigen/nmigen] whitequark daa2d6b - Deploying to gh-pages from @ 69ed4918b8b9fc8617064bbfacb92feb720006f2 🚀
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<cr1901_modern> whitequark: I figured out how to program the flash from Vivado... do you know if Vivado TCL can reset the FPGA from TCL?
<cr1901_modern> I'm reading there is no command, but I thought maybe you might know a workaround
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<_whitenotifier-f> [nmigen-boards] cr1901 synchronize pull request #111: Arty S7 OpenOCD Support - https://git.io/JUlb0
<_whitenotifier-f> [nmigen-boards] cr1901 commented on pull request #111: Arty S7 OpenOCD Support - https://git.io/JU0Ty
<_whitenotifier-f> [nmigen-boards] cr1901 edited a comment on pull request #111: Arty S7 OpenOCD Support - https://git.io/JU0Ty
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