00:08 <_whitenotifier-f> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JU2vT

00:08 <_whitenotifier-f> [YoWASP/nextpnr] whitequark 142a693 - Update dependencies.

00:43 <_whitenotifier-f> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JU2v1

00:43 <_whitenotifier-f> [YoWASP/yosys] whitequark 63a0482 - Update dependencies.

02:05 <d1b2> <Suryo> Hi! I am just getting started with nmigen on the Orange Crab FPGA and Numato Labs Mimas v2. The Orange Crab is based on lattice ECP5, and the Mimas v2 is based on Spartan 6. I was wondering if someone could point me towards resources on how to define my board in nmigen, as in where I should look and how I should proceed with it. I am familiar with verilog and have worked a little bit with both ise and vivado, but I don't have a solid background in

02:05 <d1b2> electronics or vlsi. At the present moment I'm something like a hobbyist.

04:13 <ktemkin> Suryo: if you're looking for how to come up with a platform file, there are quite a few examples in `nmigen_boards`: https://github.com/nmigen/nmigen-boards

04:14 <ktemkin> including for the OrangeCrab and Mimas (not sure if it's the v1 or v2)

04:15 <d1b2> <Suryo> Hi! Thanks for this. I've already taken a look at it. But right now, after some digging, all I'm trying to do is use the connectors defined in the Orange Crab board definition.

04:15 <ktemkin> ah, okay

04:15 <d1b2> <Suryo> Also, I'm not sure if I'm really talking to a BOT or not. But thanks!!

04:16 <d1b2> <esden> @Suryo this channel is tunneled to IRC

04:16 <ktemkin> the bot is just the IRC bridge

04:16 <d1b2> <esden> the "BOT" is just the IRC tunnel

04:16 <d1b2> <Suryo> Oh okay! Thanks for letting me know. I joined just yesterday and I don't yet know what 1bitsquared is all about haha. But thanks guys.

04:16 <d1b2> <esden> See channel descrpition 😉

04:16 <d1b2> <Kate Temkin> @Suryo same me, just over on IRC =P

04:17 <d1b2> <esden> wow TWO times KATE! WAAA

04:17 <d1b2> <Kate Temkin> I know, right?

04:17 <d1b2> <edbordin> You could call it mutipli-kate-ion

04:18 <d1b2> <esden> @edbordin LOL! You know you have to leave now right? 😛

04:18 <d1b2> <edbordin> @esden I will see myself out :D

04:18 <d1b2> <Suryo> @Kate Temkin could you point me to some resources from which I could understand how to use connectors? I'm sure that it isn't a big deal but I just can't figure it out. I spent the past two hours digging through nmigen's code on GitHub. Figured out where the connector class is defined but I haven't been able to figure out how to use the connector

04:18 <d1b2> <Kate Temkin> I'm not sure there are any resources

04:18 <d1b2> <Kate Temkin> but hold on, I'll type you up a quick thing

04:18 <d1b2> <Suryo> How are you so fast?

04:19 <d1b2> <Suryo> Like... You're typing at the speed of transmission or something.

04:19 <d1b2> <Suryo> Okay. Seems more human now.

04:20 <d1b2> <Kate Temkin> @Suryo you can refer to connectors when defining platform resources; so if you wanted to add a resource on Connector("my_connector", 0, "a1 b2 c3"), you could use "my_connector_0:0" in place of the pin name

04:20 <d1b2> <Kate Temkin> and you can dynamically add resources with platform.add_resources

04:21 <d1b2> <Suryo> Okay, and I use a platform.request to use them?

04:21 <d1b2> <Kate Temkin> yep

04:22 <d1b2> <Kate Temkin> so one simple way to grab a connector pin would be to use something like:

04:22 <d1b2> <Kate Temkin> platform.add_resources([Resource("my_resource", Pins('my_connector_0:0'), Attrs(<your attributes>))])

04:23 <d1b2> <Suryo> Ah! That just made sense.

04:23 <d1b2> <Kate Temkin> https://github.com/greatscottgadgets/luna/blob/master/luna/gateware/platform/nexys_video.py#L248 <-- here's an example of me adding some resources based on a connector definition

04:23 <d1b2> <Suryo> Wow thanks a lot!

04:24 <d1b2> <Suryo> It's getting late where I am and I have work in the morning. Thanks a lot to everyone for their help. I'll let y'all know how it goes! I'll get back to this during the day.

04:28 <d1b2> <edbordin> Ooh that's very succinct when used as intended

08:49 <agg> Suryo/ ktemkin: you can use just use the connector numbers directly and then put conn="name" inside Pins which saves a lot of typing when you have multiple pins

08:52 <agg> as I discovered like two days ago :p

09:08 <sebinho> Hi, is it still possible to have parameters for a module? The reason is integration with existing VHDL/verilog code and parameters have to be propagated as well. I understand that it is best to get rid of parameters but wanted to see whether that is an option

09:42 <agg> you can specify p_PARAMNAME="value" when instantiating, if that's what you mean

09:43 <agg> (alongside i_INPUTNAME and o_OUTPUTNAME)

09:43 <agg> like https://github.com/nmigen/nmigen/blob/master/examples/basic/inst.py#L15

09:43 <agg> (not sure if i understood your question correctly)

09:48 <jfng> sebinho: if you want to instantiate an nmigen module with parameters inside a verilog module, you can use the Yosys connect_rpc frontend

09:55 <jfng> e.g. https://github.com/jfng/riscv-formal/blob/minerva/cores/minerva/wrapper.sv#L50-L69

09:55 <jfng> which works by adding `connect_rpc -exec nmigen-rpc yosys <the full path of your Elaboratable>' to the yosys script

09:58 <sebinho> agg jfng thanks!

12:37 <_whitenotifier-f> [nmigen] jfng opened issue #501: Document how to use connectors from platform definitions - https://git.io/JU20x

13:53 <pepijndevos> uh... how do i request the pmod on the icebreaker? Or whatever it is you have to do to get the pins.

13:53 <pepijndevos> https://github.com/nmigen/nmigen-boards/blob/434702fee6f9a5c71b4cddcf6110178603fe2209/nmigen_boards/icebreaker.py#L38

13:57 <agg> pepijndevos: platform.add_resources([Resource("my_pins", 0, Pins("4 2 47 45", dir="io", conn=("pmod", 0)), Attrs(...))]); pins = platform.request("my_pins");

13:57 <agg> uhhh

13:57 <agg> pepijndevos: platform.add_resources([Resource("my_pins", 0, Pins("0 1 2 3", dir="io", conn=("pmod", 0)), Attrs(...))]); pins = platform.request("my_pins");

13:57 <agg> ....

13:57 <agg> pepijndevos: platform.add_resources([Resource("my_pins", 0, Pins("1 2 3 4", dir="io", conn=("pmod", 0)), Attrs(...))]); pins = platform.request("my_pins");

13:57 <agg> you use the pin numbers of the connector, starting from 1

13:58 <pepijndevos> ahhhh ok

13:58 <pepijndevos> ty

13:58 <agg> so, you add a new resource to your platform, and its pin numbers could just be 4 2 47 45 to use platform numbers

13:58 <agg> but since the connector is defined, you can instead use 1 2 3 4 to use the connector pin numbers, and you add conn=("pmod", 0) to use pmod 0

13:58 <agg> once that resource is added, you request and use it as normal

13:59 <agg> the - in the connectors list in the platform means to skip that number, so the available pins on one of those pmod are 1 2 3 4 7 8 9 10

13:59 <pepijndevos> I sorta assumed the connector was a resource in itself or something. This makes sense

13:59 <agg> jfng literally just opened an issue to document this better a couple of hours ago, and Suryo asked about it last night here too

13:59 <agg> (and I only tried it for the first time a few days ago, after years of using nmigen...)

14:00 <agg> it's fair to say it could be more documented :p

14:00 <agg> but yea, it does work fairly neatly once you know the magic incantation

14:01 <pepijndevos> Thanks :)

15:03 <pepijndevos> heh, I doubt a motor driver is very happy to see 12MHz PDM

15:24 <pepijndevos> so horribly confused by bit order in nmigen... I want to get the N MSB of a thing... so the last bit is MSB, right?? So... sig[:-N]?

15:25 <agg> sig[-1] gets the MSB, sig[-N] gets the Nth MSB

15:25 <agg> sig[:-N] gets bits 0, 1, 2, 3, ..., Nth MSB

15:25 <agg> (the colon implies a slice, and the missing left-hand argument implies the first item)

15:26 <agg> (similarly, sig[-N:] gets bits Nth MSB, N-1th MSB, ..., MSB, and sig[3:5] gets bits 3 and 4)

15:27 <pepijndevos> sig[-N:] is what I wanted yea, thanks :)

15:28 <agg> sorry, off by one there, the right-hand argument of the slice is exclusive, so sig[:-N] gets 0, 1, 2, 3, ..., N-1th MSB, but excludes the Nth MSB

15:28 <agg> sig[-N:] does as I described, Nth MSB, N-1th MSB, ..., MSB

15:28 <agg> (in a python shell you can always play around with this sort of thing since it's the same as normal lists)

15:29 <agg> (x = list(range(10)); x; x[-3:]; etc)

15:40 <pepijndevos> assuming you remember that 0=lsb