ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at · logs at · IRC meetings each Monday at 1800 UTC · next meeting September 14th
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<_whitenotifier-f> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1]
<_whitenotifier-f> [YoWASP/yosys] whitequark 37eac14 - Update dependencies.
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<_whitenotifier-f> [nmigen] cestrauss commented on issue #439: fsm_state changes mid cycle -
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<FL4SHK> I wish to generate a LUT in nMigen
<FL4SHK> I believe this is as simple as an `Array` of `Const`s
<FL4SHK> Does that sound right?
<FL4SHK> the LUT is for a binary search
<FL4SHK> 256 elements... don't know how many FPGA LUTs that'd use
<FL4SHK> how do I do something sequentially within one clock cycle in nMigen?
<FL4SHK> combinational logic
<FL4SHK> I believe it's as simple as making one signal and then assigning to it, with `m.d.comb`, the value of another signal
<FL4SHK> so `m.d.comb += [sig0.eq(self.bus.x), sig2.eq(sig1 + sig0)]`
<FL4SHK> hmmm
<FL4SHK> `m.d.comb += [sig0.eq(self.bus.x + self.bus.y), sig2.eq(sig1 + sig0)]`
<FL4SHK> more like this ^
<FL4SHK> does this work, btw?
<agg> it's hard to say without more context on what you're doing
<agg> but what you write will work like saying sig2.eq(sig1 + self.bus.x + self.bus.y), if that's what you mean
<agg> (i.e. all those additions will occur in the same clock cycle)
<FL4SHK> I want `sig2` to be assigned `sig1 + self.bus.x + self.bus.y`
<FL4SHK> but I want to be able to use a temporary `Signal`, which might have been assigned to within an `m.If`, for example
<FL4SHK> I want to do more than one thing in a single clock cycle
<ktemkin> you can use comb-driven signals as inputs to other comb assignments
<FL4SHK> that's what I'm after, yes
<ktemkin> just like you provided
<FL4SHK> cool, thanks
<FL4SHK> as for my LUT question, is an `Array` of `Const` the right method?
<FL4SHK> could just construct the LUT with regular Python code if so
<ktemkin> for your LUT, once you have sufficient elements, you might be better off using a Memory without a write port
<FL4SHK> I might need to read from the `Memory` and do something with the results within a single clock cycle
<FL4SHK> and my specific use case *does* need that
<ktemkin> you can set the read port's domain to "comb"
<FL4SHK> neat
<ktemkin> strictly speaking, the Array of Consts might infer an equivalent structure in the memory backend; that's pretty much how you do it in e.g. Verilog
<ktemkin> s/in the memory backend/in the synthesis backend
<FL4SHK> aI see
<ktemkin> (the Memory however, winds up directly outputting a `memrd`, which is more or less Yosys for "hey! I'm describing the read half of a memory, here!")
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<FL4SHK> seems that a priority encoder is more along the lines of what I should use.
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<FL4SHK> awygle: you around?
<FL4SHK> I'd like to know about format strings
<FL4SHK> I do use `string.format()`
<d1b2> <DX-MON> format strings take string.format(), and translates it into a prefix ('f') and braced references to variables that are in scope
<FL4SHK> I need to do a repeat operation
<d1b2> <DX-MON> all the normal rules apply, just that instead of being able to say "{}" or "{!r}" or so, you'd say "{variable}" and "{variable!r}"
<d1b2> <DX-MON> they play fine with loops as they execute as-if calling string.format() where they're written
<d1b2> <DX-MON> so if you currently say 'thing {} maps to {}'.format(a, b) for example, it'd translate into f'thing {a} maps to {b}'
<d1b2> <DX-MON> they operate identically
<d1b2> <DX-MON> I hope that makes sense?
<FL4SHK> seems that `string.format()` isn't *quite* what I was looking for here
<FL4SHK> I want to build essentially a `casez` structure
<FL4SHK> I need to build a priority encoder
<FL4SHK> `with m.Case("1--")`
<d1b2> <DX-MON> ah, indeed
<d1b2> <DX-MON> if you're able to programatically build the string, format strings might be of some use to cheapen the operation, but you are correct that they're not a magic bullet for this
<d1b2> <DX-MON> (format strings and string formatting in general is much cheaper in Python than constantly appending strings together because strings are immutable)
<awygle> FL4SHK: yes but I suspect you talked to me on discord already? What's up
<awygle> ah i see. i do something like this
<awygle> `for i in range(self._geom.banks): with m.Case(f"{i:03b}{DDR2Opcode.PrechargeBank:04b}1"): pass`
<awygle> just build the Case string programmatically with the relevant variables in an f-string format
<awygle> f-strings are fast and convenient but there's nothing wrong with string.format per se
<awygle> (i'd argue there was nothing wrong with % either tbh)
<d1b2> <ebb> I'm wary of straying into potentially sensitive topics, but what do I need to know about the difference between m-labs/nmigen and nmigen/nmigen?
<d1b2> <ebb> I understand the second one is the place to be
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<awygle> m-labs was previously funding wq's work on nmigen, as she was their employee. she's not their employee anymore and has moved the project out from under their org.
<awygle> obviously there's a lot under that but I think those are uncontroversial facts
<d1b2> <ebb> makes sense to me - thanks
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