00:50 <DaKnig> any plans to make pysim/cxxsim multithreaded?

00:51 <d1b2> <dub_dub_11> > there's an issue about PLLs on the tracker Looks like there is some info on altpll I could find and add to that 👍

01:20 <whitequark> DaKnig: nope

01:21 <whitequark> with cxxrtl in particular i believe that any sort of parallelism (other than SLP that clang etc can insert on their own) is out of scope and best handled as a part of a different project

01:21 <DaKnig> I see. simplicity is indeed important.

01:22 <whitequark> it's not even for simplicity's sake

01:22 <whitequark> but more that i do not have the necessary skills to design or maintain it

01:22 <whitequark> someone who has those is better off not being constrained by my goals

01:23 <DaKnig> what are your main goals for cxxsim and what are the contraints on it, other than your skills?

01:26 <whitequark> cxxsim or cxxrtl? those two are different

01:31 <DaKnig> cxxsim; isnt it trying to be a faster pysim? that's what I am interested in

01:33 <whitequark> cxxsim, yes

01:33 <whitequark> the way i chose to implement that is by adding cxxrtl to yosys and then using cxxrtl from python

01:33 <whitequark> this means that cxxsim de facto inherits the constraints on cxxsim

01:38 <DaKnig> cxxsim inherits the contrsints from itself?

01:39 <whitequark> the constraints on cxxrtl* sorry

04:40 <_whitenotifier-f> [nmigen-boards] ktemkin opened pull request #116: Genesys2 fixes - https://git.io/JUha0

15:05 <ronyrus> hi, if I want "SYSCONFIG xxx" to land in the generated lpf file, where and how would be the proper place and way to put it?

15:10 <ronyrus> ah, looks like toolchain overrides: add_preferences is the place.

15:38 <whitequark> yup

16:22 <FL4SHK> took a day off work

16:22 <FL4SHK> going to do 3D printing and long divider implementation stuff

16:31 <FL4SHK> I'm off tomorrow, though

16:31 <FL4SHK> different kind of off

16:31 <FL4SHK> didn't involve any PTO

16:31 <FL4SHK> specifically it's via my schedule setup

16:32 <FL4SHK> I'm off every other Friday

17:09 <_whitenotifier-f> [nmigen] H-S-S-11 commented on issue #425: Support for PLL primitives - https://git.io/JUj1l

19:04 <FL4SHK> I should make a CPU in nMigen that has non maskable interrupts

19:05 <FL4SHK> then I can use nMigen to generate NMIs

21:12 <d1b2> <dub_dub_11> further to my PLL questions earlier: how do I specify the location of the Verilog source?

21:13 <d1b2> <dub_dub_11> I've generated a PLL.v file in my quartus install location

21:13 <d1b2> <dub_dub_11> but idk how nmigen is supposed to know where to find it

21:13 <d1b2> <dub_dub_11> is it just a path?

21:15 <d1b2> <dub_dub_11> also should I be using ClockSignal, ResetSignal or just plain signals? the definition for ClockDomain indicates the latter

21:15 <Lofty> dub_dub_11: platform.add_file()

21:16 <d1b2> <dub_dub_11> ahh that makes sense

21:16 <d1b2> <dub_dub_11> ty

21:16 <Lofty> ClockSignal and ResetSignal are used to obtain the relevant signals for a domain

21:17 <Lofty> If you want to make a ClockDomain you want a plain Signal

21:20 <Lofty> That being said, what do you plan to do with the PLL? If you want to drive all your logic from it, you can use DomainRenamer to let the relevant logic use the sync domain

21:21 <d1b2> <dub_dub_11> yeah I want to drive the logic from it

21:22 <d1b2> <dub_dub_11> atm I did this by creating a new domain called sync, adding the relevant SIgnals to it then adding it to m.domains

21:23 <d1b2> <dub_dub_11> python sync = ClockDomain() clk50 = Signal() rst = Signal() m.d.comb += [ clk50.eq(platform.request("clk50")), rst.eq(platform.request("cpu_reset_n")), ] clk200 = Signal() pll_200M_0 = Instance("SIV_pll_200M", i_inclk0 = clk50, i_areset = rst, o_c0 = clk200, ) m.submodules += pll_200M_0 sync.clk = clk200 sync.rst = rst m.domains += sync

21:24 <d1b2> <dub_dub_11> with platform.add_file("C:\\intelFPGA\\18.0\\SIV_pll_200M.v", "read") above

22:56 <FL4SHK> dub_dub_11

22:56 <FL4SHK> I have a code example

22:57 <FL4SHK> I got a PLL working on my Cyclone V dev board

22:58 <FL4SHK> https://github.com/fl4shk/volt32_console

22:59 <d1b2> <dub_dub_11> ah ty

22:59 <FL4SHK> I also have VGA signal generation if you're into that

22:59 <FL4SHK> and a FIFO (though nMigen already provides a FIFO)

23:00 <d1b2> <dub_dub_11> python with open(pll_file_name) as f: platform.add_file(pll_file_name, f) ah I think my python skills are just off

23:01 <FL4SHK> were you looking at my code?

23:04 <FL4SHK> I think I want to do some cxxsim stuff