<d1b2>
<dub_dub_11> > That being said, what do you plan to do with the PLL? If you want to drive all your logic from it, you can use DomainRenamer to let the relevant logic use the sync domain @Lofty#0000 I can't find any example of this :/
<d1b2>
<dub_dub_11> only the test cases
<d1b2>
<dub_dub_11> now it's breaking the PLL 😦
<d1b2>
<dub_dub_11> the PLL has to be driven directly by an output pin
<d1b2>
<dub_dub_11> verilog always @* begin clk = 1'h0; clk = clk50_0__i; but this generated code makes it a combinational cell
<d1b2>
<dub_dub_11> so it can't synthesise
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<_whitenotifier-f>
[nmigen/nmigen-boards] ktemkin 0e95118 - genesys2: convert `ulpi` to ULPIResource
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<d1b2>
<dub_dub_11> compiling for Cyclone V still creates these LUTs in the clock path, but the newer PLLs don't seem to mind being driventhrough a comb block
<d1b2>
<dub_dub_11> so I guess it's partly a quartus issue for inferring LOGIC_CELL_COMB blocks from the buffers
<d1b2>
<dub_dub_11> but also the generated nmigen code is causing a problem by confusing quartus
<d1b2>
<dub_dub_11> even if a request a pin, it still ends up with buffers
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<d1b2>
<dub_dub_11> Quartus automatically puts input buffers, so I don't think it is necessary to explicitly instantiate them (and they seem to be causing this issue)
<d1b2>
<dub_dub_11> or at least there needs to be a way to bypass it
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<awygle>
i wonder if it would be beneficial to have a tracking issue for the most important docs things
<awygle>
most important and/or least discoverable
<awygle>
that could serve as both tracking and as a stopgap place to direct people when they have questions about the top 5 or so most common things
<awygle>
(this is inspired by telling dub_dub_11 about dir='-' out of band, re: the above convo)
<d1b2>
<dub_dub_11> when I compiled for a cyclone V and checked the technology map, it had the same issue that the input clock went through LUTs and into the PLL. The only reason it worked is because Cyclone V allows this but Stratix IV doesn't, so it might be worth changing IntelPlatform
<d1b2>
<dub_dub_11> so that when the default_clock is requested it uses dir="-"
<awygle>
Lofty: ^ thoughts? you're the expert here
<Lofty>
Uuuuuuh
<Lofty>
Brain no worky rn
<Lofty>
... Yeah, uh. I'm Ravenslofty#9170 on Discord, you can poke me there, and maybe I'll remember to respond
<Lofty>
I know there are other problems with I/O buffers, but nMigen kinda requires them in various cases
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<FL4SHK>
now that I'm done *finally* getting my 3D printer level and working
<FL4SHK>
I'm going to finally finish my long udiv module
<FL4SHK>
should end up being pretty fast (other than the fact that it won't be pipelined)