03:02 <emeb_mac> Earlier today I got some help on multiple clock domains. I think I've got a simple example working but wanted to check if it makes sense to the experts. Comments / critique appreciated: https://pastebin.com/BhqKq1Av

06:38 <lkcl_> emeb: as i said, you're missing the reset signal.

06:39 <lkcl_> when you convert to ilang (or verilog) you will find a disconnected signal named "sync_two_rst"

06:40 <lkcl_> you need sync2.rst.eq(ResetSignal())

10:45 <jeanthom> hi there!

14:26 <emeb> lkcl_: yep - good point.

14:27 <whitequark> you can also use a reset-less domain if that fits you better

14:28 <whitequark> it depends on the use case, on FPGAs often global reset is unnecessary

14:28 <whitequark> since you have a nice power-on reset right there

15:02 <emeb> playing around with a generated reset -> https://pastebin.com/DkRFfshH

15:04 <emeb> which looks like this: https://www.dropbox.com/s/whywmydhz8rapfm/gen_rst.png?dl=0

18:09 <_whitenotifier-b> [nmigen-boards] jeanthom opened pull request #100: versa_ecp5: Fix DDR3 IO types - https://git.io/JJXYI

18:13 <_whitenotifier-b> [nmigen-boards] whitequark closed pull request #100: versa_ecp5: Fix DDR3 IO types - https://git.io/JJXYI

18:13 <_whitenotifier-b> [nmigen/nmigen-boards] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JJXYC

18:13 <_whitenotifier-b> [nmigen/nmigen-boards] jeanthom f26a729 - versa_ecp5: Fix DDR3 IO types, using the types from Lattice's DDR3 demo lpf

19:41 <d1b2> <emeb> Part of the "learn nmigen" excercise has been translating some old verilog over. I'm synthesizing both designs and comparing the results. For some reason the nmigen output runs about 40% faster but is also about 25% larger. It'll be interesting to dig in to the output and figure out why.