ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each Monday at 1800 UTC · next meeting August 17th
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<_whitenotifier-3> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±2] https://git.io/JUvXU
<_whitenotifier-3> [YoWASP/nextpnr] whitequark 09c5b60 - Update dependencies.
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<_whitenotifier-3> [nextpnr] github-actions[bot] opened pull request #10: Release current development snapshot to PyPI - https://git.io/JUv1W
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<_whitenotifier-3> [nextpnr] whitequark closed pull request #10: Release current development snapshot to PyPI - https://git.io/JUv1W
<_whitenotifier-3> [YoWASP/nextpnr] whitequark pushed 3 commits to release [+1/-0/±3] https://git.io/JUv1E
<_whitenotifier-3> [YoWASP/nextpnr] whitequark 23d77cf - [skip ci] Don't require maintainer action for updating the develop branch.
<_whitenotifier-3> [YoWASP/nextpnr] whitequark 3ce5cc9 - [skip ci] Automatically create PRs from develop to release.
<_whitenotifier-3> [YoWASP/nextpnr] whitequark f90d88c - Update dependencies.
<_whitenotifier-3> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±2] https://git.io/JUv1a
<_whitenotifier-3> [YoWASP/yosys] whitequark 0559c24 - Update dependencies.
<_whitenotifier-3> [yosys] github-actions[bot] opened pull request #14: Release current development snapshot to PyPI - https://git.io/JUv11
<ktemkin> I can’t remember: do I use FHDLTestCase, really, or do I mostly use it as a base class?
<ktemkin> I’d be fine just implementing an equivalent in LUNA.
<ktemkin> (I‘m self-restrained from using my computer for these kinds of Work Things on Fri/Sat/Sun)
<ktemkin> ... can’t properly seem to ignore github chatter, though >.>
<miek> ktemkin: yeah, it's just as a base class. also it looks like you're not using anything from it, all the tests still pass after changing LunaGatewareTestCase to base off unittest.TestCase
<ktemkin> yeah, that’s the right fix; I think I just imagined that
<ktemkin> er
<ktemkin> imagined that subclasses might want FHDLTestCase methods
<ktemkin> I’ll swap that on Monday, unless someone wants to PR it first
<_whitenotifier-3> [yosys] whitequark closed pull request #14: Release current development snapshot to PyPI - https://git.io/JUv11
<_whitenotifier-3> [YoWASP/yosys] whitequark pushed 1 commit to release [+0/-0/±2] https://git.io/JUvD9
<_whitenotifier-3> [YoWASP/yosys] whitequark 882a957 - Update dependencies.
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<tpw_rules> is there a way to repeat a signal to do sign extension
<d1b2> <TiltMeSenpai> dirty way would be something like Cat(*[sig for sig in range(n)]) (that can be optimized)
<d1b2> <TiltMeSenpai> the * isn't needed if Cat can take an iterable of signals
<tpw_rules> i mean in that case i can just do *([sig]*24)
<d1b2> <TiltMeSenpai> yeah. I assume you're asking for the not-dirty way?
<tpw_rules> yeah i had some vague memory of a Rep thing?
<tpw_rules> maybe i made it up
<d1b2> <TiltMeSenpai> that sounds familiar
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<d1b2> <TiltMeSenpai> oh I think it's Repl
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<tpw_rules> bingo. thank you
<d1b2> <TiltMeSenpai> np
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<miek> there's a nicer workaround mentioned in the issue btw https://github.com/nmigen/nmigen/issues/464
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<lkcl_> tpw_rules: Repl. Repl(sig, 24) 1 sec...
<lkcl_> tpw_rules: https://git.libre-soc.org/?p=nmutil.git;a=blob;f=src/nmutil/extend.py;hb=HEAD
<lkcl_> those are the macros/functions we're currently using whilst sign/zero-extend is resolved
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<_whitenotifier-3> [nmigen] anuejn opened issue #485: {r,w}_level is broken on AsyncFIFO{Buffered,} - https://git.io/JUfOp
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<tpw_rules> is there a way to do .eq combinatorially in a test? so i don't have to change it back next cycle?
<whitequark> not really
<whitequark> (ha, that's a verilog feature: force/release)
<tpw_rules> so there's no way from yield pulse.eq(1); yield; yield pulse.eq(0).
<whitequark> you can run another process
<whitequark> but it's not quite what you want
<tpw_rules> is it possible to add processes in the middle of simulation or yield new ones?
<tpw_rules> i guess if you did that then you couldn't do it two cycles in a row for the same signal
<whitequark> it is possible to add processes in the middle of a simulation
<whitequark> though you can't do it by yielding
<_whitenotifier-3> [nmigen] awygle commented on issue #485: {r,w}_level is broken on AsyncFIFO{Buffered,} - https://git.io/JUfnW
<_whitenotifier-3> [nmigen] awygle commented on issue #484: Explicit deprecation/removal notice for FHDLTestCase - https://git.io/JUfng
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<Yehowshua> Some time ago I saw some verilator example by Gisselquist I think where he mapped the verilator model to some X screen buffer
<Yehowshua> Is it possible to make a "fake" luna device in that sense?
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<Lofty> Yehowshua: it's probably equivalent to a cxxrtl black box
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