<lkcl>
DaKnig: not entirely sure what it's for, however look in nmigen/build/plat.py there is a function "create_missing_domain" which uses ResetSynchronizer
<lkcl>
although it is an internal function it may give some clues
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<lkcl>
ha, create_missing_domains is the function being called :)
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<lkcl>
DaKnig, ahh.... you're gonna find this very odd: change the name from cd_40 to cd40
<DaKnig>
tbh I am not sure why the person who did this put the input clock just to get the same one out
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<DaKnig>
ok nice
<DaKnig>
thanks
<DaKnig>
it seems like just removing those lines that generate the unnecessary clocks is enough
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<DaKnig>
ok now I have another problem
<DaKnig>
it says that the io standard was not specified
<DaKnig>
for what wire? I dont know. I assume it's the PMOD connector.
<DaKnig>
how should I do this?
<DaKnig>
add the Attrs to each subsignal in the resource that describes the connected board?
<vup>
you can also add "Attrs" to a Resource directly
<vup>
also generating a clock with the same frequency as the input clock from a PLL could used to have a fixed phase relation between the output clocks
<DaKnig>
aha
<DaKnig>
I thought the output clocks are phase locked to the input clock anyways though?
<vup>
True, but it has a absolute phase shift
<vup>
Not sure how big it is for the 7series pll though
<Degi>
Is "IndexError: Cannot index 15 bits into 15-bit value" a bug? I think it should say "IndexError: Cannot index 16 bits into 15-bit value" since the index is zero-based but 'bits' language-wise should be 1 based.
<DaKnig>
"index 1 bits into 1-bit value"
<DaKnig>
sounds about right to me
<Degi>
Hmh, doesnt the 1 bit value have only one bit which can be indexed? (not 0)
<DaKnig>
I mean, you can index "0 bits into 1-bit value", but not "1 bits into 1-bit value"
<DaKnig>
to me that sounds alright
<Degi>
Hmm
<DaKnig>
but then again, Im not in charge
<Degi>
What does "index n bits into a x bit value" mean?
<DaKnig>
this is an engineer tool; language doesnt have to make sense :-)
<Degi>
I mean I get that it says that since it is 0-indexed but it kinda sounds weird tbh
<DaKnig>
I would prefer a "gramatically incorrect" answer that makes sense in terms of programming since well, I am writing my code 0-based and anything else would distract me from that
<Degi>
I mean x[15] is still the 16th bit of x hmm. Maybe formulating it as "IndexError: Index 15 is out of range for a 15-bit value"
<DaKnig>
it is the 16th bit but it's index 15
<DaKnig>
yeah maybe saying that would be more correct.
<Degi>
Yes, '15 bits' sounds like it means the 15th bit and that has caused some confusion for me, specifying that the index 15 is meant would make that clear.
<whitequark>
Degi: feel free to open an issue about it
<Degi>
Okay
<whitequark>
DaKnig: "why" is a totally reasonable question; any decent specification or doc has a "rationale" section
<Degi>
Oh, what happened to the issue I tried to post... Should not have clicked on notifications.
<cr1901_modern>
whitequark: Do you want me to handle the "no .." as part of PRs, or do you want to do it later?
<cr1901_modern>
the PR*
<_whitenotifier-3>
[nmigen] ECP5-PCIe opened issue #488: Change error message for IndexError for increased clarity - https://git.io/JUU6R
<whitequark>
cr1901_modern: oh, it's not merged yet? then as a part of the PR
<cr1901_modern>
ack
<whitequark>
DaKnig: regarding "ilang" vs "RTLIL", I asked Claire
<whitequark>
>I'm absolutely okay with renaming the commands. (Currently "ilang" is the text language and "RTLIL" the data structure. It's an astonishingly pointless distinction.)
<whitequark>
awygle: you were right :p
<_whitenotifier-3>
[nmigen] cr1901 synchronize pull request #461: SSH Client Support via Paramiko - https://git.io/JJarq
<cr1901_modern>
Hmmm, not that I'm complaining, but I thought pushing after approval causes approval to be reset
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<DaKnig>
how can I add clk of sync domain to the output of the simulation?
<DaKnig>
the wave file, I mean.
<whitequark>
should already be there
<whitequark>
do you not see it in gtkwave? nowhere in hierarchy?
<DaKnig>
dont see it in the configuration loaded from the .gtkw file
<whitequark>
oh
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<whitequark>
you're not creating the sync domain explicitly, right?
<DaKnig>
right
<DaKnig>
if it matters at all- I dont have any process attached
<DaKnig>
since the circuit has no input (besides clk and rst
<DaKnig>
I think the sim should , when it starts to run, output all clock domain clocks and resets to the gtkwave
<DaKnig>
should I make an issue?
<agg>
cr1901_modern: it's a GitHub option per repo whether pushes clear existing reviews
<cr1901_modern>
ahhh
<whitequark>
agg: hm i should turn that on
<Sarayan>
The cyclone shows me something annoying with single-clock-and-enables: you can't use the dedicated clock routes to move enable signals afaict
<DaKnig>
I think I'll make an issue about the clock domain underscore weirdness
<whitequark>
sure, go ahead
<whitequark>
i'll take a look later
<FL4SHK>
whew, that was an episode
<Sarayan>
it also has the capability of inverting clocks before the ff, but you can't really use that either
<whitequark>
agg: can't find it
<FL4SHK>
finally got a new OS installed on my laptop
<FL4SHK>
the existing Arch Linux installation I had wouldn't let me log in even after a `passwd root` command I ran in a chroot
<FL4SHK>
now I can use my laptop again!
<DaKnig>
nice
<agg>
whitequark: checkbox under branch protection settings iirc
<whitequark>
oh
<agg>
After "require reviews" is ticked
<whitequark>
ok that's kinda different
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<agg>
Yea, not at a pc right now so couldn't check exact details but I think that's the setting that controls the behaviour cr1901_modern was thinking of
<_whitenotifier-3>
[nmigen] DaKnig opened issue #489: nMigen doesn't like clock domains with underscores - https://git.io/JUUDq
<_whitenotifier-3>
[nmigen] DaKnig edited issue #489: nMigen doesn't like clock domains with underscores - https://git.io/JUUDq
<agg>
DaKnig: it's not the underscore, starting a cd name with "cd_" is handled differently and only the part after cd_ is considered iirc
<agg>
(in other words changing cd_x to dd_x should also fix your issue, but better to just name the cd without a cd prefix, this feature allows the python binding to have the prefix while naming the clock domain itself without it)
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<_whitenotifier-3>
[nmigen] whitequark commented on issue #489: nMigen doesn't like clock domains with underscores - https://git.io/JUUD4
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<DaKnig>
agg: should use the more common way to have "magic global names" - in C that'd be prefixing the thing with _nmigen_cd and in python either _cd or __cd
<DaKnig>
that is very unexpected
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<DaKnig>
cc lkcl
<DaKnig>
here's the reason
<whitequark>
it's not magic (moreso than any other names in nmigen) or global
<agg>
It wouldn't be appropriate to use _cd in context anyway, it's not meant to be private
<agg>
I think maybe the confusion here is because you were explicitly specifying a name starting with cd_ rather than using the automatic naming from the binding name
<agg>
It's less surprising that "cd_io = ClockDomain()" creates a cd named "io" than that "x = ClockDomain("cd_io")" does too, perhaps
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<awygle>
yaaaay i was right :p
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<DaKnig>
how can I use pypy with nmigen? for some reason it doesnt recognize nmigen at all
<DaKnig>
"No module named 'nmigen'"
<whitequark>
pypy has a different, separate set of installed packages