ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each Monday at 1800 UTC · next meeting August 24th
<awygle> what is the `.[builtin-yosys]` syntax on the pip commands in the install instructions?
<awygle> is that like cargo features?
<_whitenotifier-3> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JULn2
<_whitenotifier-3> [YoWASP/yosys] whitequark f303311 - Update dependencies.
<whitequark> awygle: yes, except worse
<awygle> i assumed (even though features are like the third worst thing about cargo)
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<_whitenotifier-3> [nmigen] whitequark commented on issue #492: How do you make a bounded up-down counter without modulo? - https://git.io/JULWM
<_whitenotifier-3> [nmigen] whitequark edited a comment on issue #492: How do you make a bounded up-down counter without modulo? - https://git.io/JULWM
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<awygle> https://fires.im/ speaking of simulators
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<whitequark> wait, isn't it the one i linked earlier?
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<ktemkin> jeez, every time I go to port code from oMigen I find yet another collection of undocumented grab-bag style miscellanea in it >.>
<whitequark> yup
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<cr1901_modern> whitequark: Does this look fine as-is/could you approve it? https://github.com/nmigen/nmigen/pull/493
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<revolve> whitequark: what verilog compiler do you use on linux?
<revolve> or phrased another way, is icarusverilog any good or would you recommend something else?
<DaKnig> revolve: is this question only targetted at wq?
<revolve> nah I'm open to everyone's thoughts on this
<revolve> DaKnig: do you know of owt better than icarusverilog on linux?
<Lofty> revolve: Check out cxxsim
<Lofty> It compiles the nMigen code to C++, and then executes that
<Lofty> Since it's going through Yosys, you can use any synthesisable Verilog, or even VHDL through the GHDL plugin
<revolve> Thank you!
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<agg> revolve: verilator is also commonly used to both simulate verilog and even just to lint it
<agg> If you're starting with verilog you probably want cxxrtl (part of yosys, simulates verilog) instead of cxxsim (part of nmigen, uses cxxrtl to simulate nmigen)
<revolve> Thanks for hipping me to verilator and cxxrtl, agg. you rock m8
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<_whitenotifier-3> [nmigen] whitequark closed pull request #493: Add documentation for how to set up NMIGEN_ENV_Diamond on Windows. - https://git.io/JUI4Y
<_whitenotifier-3> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/JULpP
<_whitenotifier-3> [nmigen/nmigen] cr1901 47ecc16 - vendor.lattice_{ecp5,machxo_2_3l}: explain how to set up NMIGEN_ENV_Diamond on Windows.
<whitequark> Lofty: tbh using the GHDL plugin with cxxsim might be a bit challenging
<_whitenotifier-3> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JULpy
<_whitenotifier-3> [nmigen/nmigen] whitequark 5dc9d7d - Deploying to gh-pages from @ 47ecc162839be81c1d9256f9ffd53a5f1ab3864a 🚀
<Lofty> How so? Is it that the input netlist looks quite different to what read_verilog would generate?
<whitequark> nono
<whitequark> it's the cxxsim part that's a problem
<whitequark> it's not very customizable out of the box. really, it's just... not customizable
<Lofty> I see
<whitequark> that's, of course, fixable
<Lofty> (also, thanks for the RT)
<whitequark> np
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<cr1901_modern> ty wq. Now I can check that off my todo list, which is growing faster than shrinking :)
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<_whitenotifier-3> [nmigen] sam-falvo opened issue #494: Strange behavior when asserting an output signal - https://git.io/JUtIg
<_whitenotifier-3> [nmigen] sam-falvo commented on issue #494: Strange behavior when asserting an output signal - https://git.io/JUtI9
<_whitenotifier-3> [nmigen] sam-falvo closed issue #494: Strange behavior when asserting an output signal - https://git.io/JUtIg
<DaKnig> I wonder how many of those I made :)
<DaKnig> bang your head against the wall for hours, then decide its a bug with the tool; then find my own mistake just after posting the issue.
<DaKnig> can I expect nmigen+backend to expand multiplication by constant into the more efficient adder?
<DaKnig> as in, x*10 -> (x+x<<2)<<1 or whatever
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<whitequark> DaKnig: yeah