<awygle>
i assumed (even though features are like the third worst thing about cargo)
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<_whitenotifier-3>
[nmigen] whitequark commented on issue #492: How do you make a bounded up-down counter without modulo? - https://git.io/JULWM
<_whitenotifier-3>
[nmigen] whitequark edited a comment on issue #492: How do you make a bounded up-down counter without modulo? - https://git.io/JULWM
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<Lofty>
It compiles the nMigen code to C++, and then executes that
<Lofty>
Since it's going through Yosys, you can use any synthesisable Verilog, or even VHDL through the GHDL plugin
<revolve>
Thank you!
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<agg>
revolve: verilator is also commonly used to both simulate verilog and even just to lint it
<agg>
If you're starting with verilog you probably want cxxrtl (part of yosys, simulates verilog) instead of cxxsim (part of nmigen, uses cxxrtl to simulate nmigen)
<revolve>
Thanks for hipping me to verilator and cxxrtl, agg. you rock m8
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<_whitenotifier-3>
[nmigen] whitequark closed pull request #493: Add documentation for how to set up NMIGEN_ENV_Diamond on Windows. - https://git.io/JUI4Y
<_whitenotifier-3>
[nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/JULpP
<_whitenotifier-3>
[nmigen/nmigen] cr1901 47ecc16 - vendor.lattice_{ecp5,machxo_2_3l}: explain how to set up NMIGEN_ENV_Diamond on Windows.
<whitequark>
Lofty: tbh using the GHDL plugin with cxxsim might be a bit challenging
<_whitenotifier-3>
[nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JULpy
<_whitenotifier-3>
[nmigen/nmigen] whitequark 5dc9d7d - Deploying to gh-pages from @ 47ecc162839be81c1d9256f9ffd53a5f1ab3864a 🚀
<Lofty>
How so? Is it that the input netlist looks quite different to what read_verilog would generate?
<whitequark>
nono
<whitequark>
it's the cxxsim part that's a problem
<whitequark>
it's not very customizable out of the box. really, it's just... not customizable
<Lofty>
I see
<whitequark>
that's, of course, fixable
<Lofty>
(also, thanks for the RT)
<whitequark>
np
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<cr1901_modern>
ty wq. Now I can check that off my todo list, which is growing faster than shrinking :)
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<_whitenotifier-3>
[nmigen] sam-falvo opened issue #494: Strange behavior when asserting an output signal - https://git.io/JUtIg
<_whitenotifier-3>
[nmigen] sam-falvo commented on issue #494: Strange behavior when asserting an output signal - https://git.io/JUtI9
<_whitenotifier-3>
[nmigen] sam-falvo closed issue #494: Strange behavior when asserting an output signal - https://git.io/JUtIg
<DaKnig>
I wonder how many of those I made :)
<DaKnig>
bang your head against the wall for hours, then decide its a bug with the tool; then find my own mistake just after posting the issue.
<DaKnig>
can I expect nmigen+backend to expand multiplication by constant into the more efficient adder?