I'm using AsyncFIFOBuffered on ECP5, 16b wide, 4096+1 words deep, and my design is struggling to get above 100MHz. Is this simply the harsh reality of the ECP5 BRAM or can I do something to speed up the design?
ECP5 bram is pretty slow for non 5G parts
5-6ns clock to out
daveshah: really? they put faster RAM on the ECP5G?
which I mean as semantically distinct from "I'm working on PCIe"
That leaves it up to interpretation whether it's a good or bad flavor.
awygle: I'm not doing anything with a structured end-goal with it, but I've been mentoring Degi in implementing it, and I can't look at anything sufficiently complicated without getting drawn into it
i'll look into that as a part of the docs effort
DaKnig: also: generically, python lets you stick whatever you want to into its indexing operator  (see e.g. __getitem__); though individual types like list impose their own meanings and thus requirements