ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each 1st & 3rd Monday at 1800 UTC · next meeting July 6th
<Falteckz> Got it - though perhaps not difficult to add a metastability warning in the future
<whitequark> it's not entirely trivial
<whitequark> mostly because of instances
<Falteckz> I don't understand the problem domain, I don't understand how nMigen works under the public API. I don't mean to trivialise the problem, only that I hope it can be solved :)
<whitequark> the problem is that if you instantiate some verilog or vendor primitives you don't know which domain the inputs and outputs belong to
<Falteckz> Ah yes, I see. Having only worked with the ICE40LP*8k/CM81 so far. There are very few vendor primatives other than IO and PLL blocks. So it's not something I've encountered or give consideration to.
<whitequark> yep
<awygle> whitequark: so the SRAMResource in nmigen-boards inverts some pins with PinsN (cs, oe, we) but not others (dm). is there some way we can make this clearer when using the resource? i just burned a fair bit of time on this (oops)
<Falteckz> When you emit a vendor primative from nMigen, is the Verilog just templated through? I would have thought some sort of "Resource" object would be created that clearly defines inputs and outputs. Perhaps my lack of experience with primatives means I just don't understand the edge cases (or face cases I guess)
<Stary> yeah, i've burned some time on sdramresource inverting its control pins (i was matching the datasheet, which uses !cs etc)
<whitequark> awygle: hm
<whitequark> should dm be inverted?
<whitequark> if it's not inverted that's probably just a bug
<awygle> i dunno, on this SRAM "dm" is ~UB and ~LB
<awygle> which matches the comment, saying "dm = #UB, #LB"
<whitequark> let me rephrase
<whitequark> would you have lost less time if dm used PinsN?
<awygle> no, probably not
<awygle> i only noticed dm not being inverted when i discovered oe, etc being inverted
<awygle> in retrospect it makes total sense that they are, it just caused me to wonder if it'd make more sense to request negation or not when instantiating the resource or something
<whitequark> okay so the idea is that if you use platform, 1 = active. always. regardless of what the hardware does
<whitequark> among other things this has the nice effect that requesting and not using a pin means you don't activate anything
<whitequark> because toolchains tend to tie unused pins to 0
<whitequark> so if you had say three SPI devices on a bus you could get a bus conflict if you requested and then not used CS#
<whitequark> but since you request CS (inverted) it's ok
<awygle> mhm
<whitequark> i admit that it's possible that the novelty factor makes this not worth it
<whitequark> so far this seems to surprise people exactly once
<whitequark> so i'm not yet convinced that it's bad
<whitequark> i mean, "1 = inactive" is also a gotcha... it's just one that most of us learned long ago
<awygle> i don't hate the idea in principle, but i don't love having to go to nmigen-boards to look up the definition of an SRAMResource to figure it out. perhaps the problem really comes from "some SRAMs have active high data masks, some have active low byte masks".
<whitequark> another thing
<whitequark> wait what
<whitequark> is that really the case?
<awygle> well the SRAMResource is defined with "cs" and "dm", where dm is active high
<whitequark> yes
<awygle> and my SRAM is defined with ce and lb/ub, which are all active low
<whitequark> argh
<whitequark> which SRAMs have active high LB/UB?
<awygle> i don't know for sure that a cs/dm sram exists but i assume it does because somebody made the resource after it
<whitequark> er
<whitequark> i made that resource
<awygle> do you remember what you based it on/
<whitequark> yeah and it had LB/UB
<whitequark> let me find it
<awygle> http://www.issi.com/WW/pdf/61-64WV6416BLL.pdf this is mine, for the record
<whitequark> ... hang on
<whitequark> there are no in-tree targets that use dm=
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<whitequark> awygle: ok so the answer is that i just fucked up
<whitequark> can you modify the SRAMResource so that it has the proper data mask polarity?
<awygle> yeah sure
<whitequark> i probably did it based on some theoretical SRAM chip
<whitequark> so to recap
<awygle> guessing we want to keep "cs" as "cs" and not as "ce"?
<whitequark> you're saying that dm=0b11 should enable both bytes, dm=0b01 should enable low byte, right?
<awygle> yes
<whitequark> yep, i fucked up, i should've used PinsN
<whitequark> regarding CS, have you ever seen an SRAM with CS?
<whitequark> I might have just copy-and-pasted it
<awygle> i haven't but i haven't used a ton of SRAMs
<whitequark> ah, wait, hm
<whitequark> i remember now
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<whitequark> i think i had this idea to standardize a bit on pin names, similar to pin polarities
<whitequark> so clock is always "clk", clock enable is always "clk_en", address is always "a"
<whitequark> i am a lot less attached to that decision than to having PinsN
<whitequark> so if you think SRAMResource is better off with ce instead of cs, we can do that
<awygle> i do, but i'd really like to ask the audience if possible
<awygle> think you could tweet the question?
<whitequark> mhh i don't feel ready to parse all the replies right now
<whitequark> maybe later
<awygle> fair nough
<awygle> i'll do the pinsn thing
<whitequark> already done
<whitequark> let me push
<awygle> oh ok nvm then
<awygle> i don't even have a PR fork of nmigen-boards yet so that's convenient
<_whitenotifier-f> [nmigen/nmigen-boards] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JJUWx
<_whitenotifier-f> [nmigen/nmigen-boards] whitequark 95c1760 - [breaking-change] resources.memory: add missing inversion on SRAMResource(dm=).
<whitequark> sorry about the wasted time
<whitequark> ... so, i tried three 'optimizations' for pysim. all of which made it significantly slower
<whitequark> one by a factor of 8 lmao (converting AoS to SoA)
<d1b2> <Darius> "I do not think that word means what you think it means"
* awygle is currently converting AoS to SoA
<whitequark> oh okay so i dod AoS to SoA conversion correctly now
<whitequark> now it's just 20% faster i guess
<awygle> nice!
<whitequark> the problem is that the prerequisite for converting to either AoS or SoA makes it 3 times as slow in first place
<whitequark> it's kind of an obnoxious problem
<whitequark> aligning the ways pysim and cxxsim work
<whitequark> so they can share simulation state
<awygle> mm
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<_whitenotifier-f> [nmigen/nmigen] whitequark pushed 1 commit to master [+1/-1/±0] https://git.io/JJUlE
<_whitenotifier-f> [nmigen/nmigen] whitequark b4ecee1 - back.{cxxrtl→_cxxrtl}: privatize.
<_whitenotifier-f> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±12] https://git.io/JJUlz
<_whitenotifier-f> [nmigen/nmigen] whitequark 87aa801 - Deploying to gh-pages from @ b4ecee142eaf8cfbce194ef379c5537a15c86dca 🚀
<_whitenotifier-f> [nmigen/nmigen] whitequark created branch master https://git.io/JJUlM
<_whitenotifier-f> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±12] https://git.io/JJUlD
<_whitenotifier-f> [nmigen/nmigen] whitequark 06102ab - Deploying to gh-pages from @ 14845af235eb815e8529796833d6a394c54205ab 🚀
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<whitequark> hm
<whitequark> should the code to run a cxxrtl design be a part of back.cxxrtl, or sim.cxxsim
<whitequark> maybe the former? loading the .so is necessary for introspection
<Falteckz> Default states for vendor blocks are bitstream configurable, does PnR take care of defaults behind the scenes when not specified?
<Falteckz> s/configurable/configurable sometimes/
<whitequark> what do you mean?
<whitequark> by default states that is
<Falteckz> Sorry I mean unconnected ports on a vendor block
<awygle> they'll mostly get optimized away
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<Falteckz> Clearly I need my own bouncer -.-
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<_whitenotifier-f> [nmigen] jeanthom opened issue #419: nMigen-Yosys isn't detected by require_tool - https://git.io/JJUoG
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<d1b2> <286Tech> Now with color! \o/
<TD-Linux> reimu is not a hat!!!
<d1b2> <286Tech> That's what Marisa is wondering.
<d1b2> <286Tech> I messed up the colors a bit, so here are some more examples with fixed colors: https://twitter.com/BitlogIT/status/1278642403386195968
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<_whitenotifier-f> [nmigen] whitequark commented on issue #419: nMigen-Yosys isn't detected by require_tool - https://git.io/JJUbI
<_whitenotifier-f> [nmigen] whitequark commented on issue #419: nMigen-Yosys isn't detected by require_tool - https://git.io/JJUbR
<_whitenotifier-f> [nmigen] whitequark commented on issue #419: nMigen-Yosys isn't detected by require_tool - https://git.io/JJUNv
<_whitenotifier-f> [nmigen] jeanthom commented on issue #419: nMigen-Yosys isn't detected by require_tool - https://git.io/JJUNI
<_whitenotifier-f> [nmigen] jeanthom closed issue #419: nMigen-Yosys isn't detected by require_tool - https://git.io/JJUoG
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<_whitenotifier-f> [nmigen] whitequark commented on issue #419: nMigen-Yosys isn't detected by require_tool - https://git.io/JJUNW
<_whitenotifier-f> [nmigen] whitequark edited a comment on issue #419: nMigen-Yosys isn't detected by require_tool - https://git.io/JJUNW
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<_whitenotifier-b> [nmigen/nmigen] whitequark pushed 1 commit to cxxsim [+1/-0/±0] https://git.io/JJUjt
<_whitenotifier-b> [nmigen/nmigen] whitequark 3b9cb5e - wip
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<_whitenotifier-b> [nmigen] jeanthom commented on issue #419: nMigen-Yosys isn't detected by require_tool - https://git.io/JJTeJ
<_whitenotifier-b> [nmigen] jeanthom reopened issue #419: nMigen-Yosys isn't detected by require_tool - https://git.io/JJUoG
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<FL4SHK> gonna make an SDRAM controller
<FL4SHK> ...after I make a scope
<FL4SHK> I've got my FIFO-based VGA signal generation working
<FL4SHK> the scope needs, uh, some graphics
<FL4SHK> I don't know what size font to use
<FL4SHK> I'll open source them both
<FL4SHK> oh boy
<FL4SHK> `can't place node "sdram_0__cs__io" -- illegal location assignment PIN_G7`
<FL4SHK> whitequark: ^
<FL4SHK> awygle: ^
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<awygle> what board are you using?
<awygle> FL4SHK:
<_whitenotifier-b> [nmigen] whitequark commented on issue #419: nMigen-Yosys isn't detected by require_tool - https://git.io/JJTvH
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<FL4SHK> awygle: DE0-CV
<whitequark> sounds like a bug in the board file
<FL4SHK> yes
<FL4SHK> also, future plan for me: DDR3 controller
<FL4SHK> I want to get an SDRAM controller built first
<awygle> pin G7 is ground, so yeah
<awygle> board file is wrong
<awygle> oh wait no, i take that back, i was looking at the wrong package
<FL4SHK> also, I can't seem to find what the SDRAM's model is
<FL4SHK> so I can't find the datasheet...
<FL4SHK> ah, looking at the board got it
<miek> there's a table in the DE0-CV user manual. from a quick glance, i think the BA pins are wrong too - should be T7,AB7
<_whitenotifier-b> [nmigen/nmigen] whitequark pushed 1 commit to cxxsim [+1/-0/±0] https://git.io/JJTJw
<_whitenotifier-b> [nmigen/nmigen] whitequark 0c33bf4 - wip
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<FL4SHK> I think I'm going to be able to get this SDRAM controller working today...
<FL4SHK> but I need nmigen-boards fixed first
<FL4SHK> the data sheet is helpful
<_whitenotifier-b> [nmigen] whitequark commented on issue #418: Simulation of Verilog output doesn't match nMigen simulation - https://git.io/JJTUO
<_whitenotifier-b> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±6] https://git.io/JJTUw
<_whitenotifier-b> [nmigen/nmigen] whitequark 6bfff25 - vendor: `yosys` is not a required tool for proprietary toolchains.
<_whitenotifier-b> [nmigen] whitequark closed issue #419: nMigen-Yosys isn't detected by require_tool - https://git.io/JJUoG
<_whitenotifier-b> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±12] https://git.io/JJTU6
<_whitenotifier-b> [nmigen/nmigen] whitequark 4d6a02e - Deploying to gh-pages from @ 6bfff25e7614399a3e660f72d964e100172e9416 🚀
<_whitenotifier-b> [nmigen/nmigen] whitequark pushed 1 commit to master [+2/-2/±2] https://git.io/JJTTs
<_whitenotifier-b> [nmigen/nmigen] whitequark 369bc3e - _yosys→_toolchain.yosys
<_whitenotifier-b> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±12] https://git.io/JJTTc
<_whitenotifier-b> [nmigen/nmigen] whitequark e07c114 - Deploying to gh-pages from @ 369bc3e30721eb48e4425c8951cf9d99a4ab7e18 🚀
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<whitequark> awygle: poke
<awygle> whitequark: 20minutes
<whitequark> i think i'm going to fork sphinxcontrib-contentui to focus specifically on showing different docs for different platforms
<whitequark> any naming suggestions?
<whitequark> "sphinxcontrib-platformtabs"?
<whitequark> "sphinxcontrib-platformpicker"?
* hell__ thinks of "sphinxcontrib-archooser", but this name doesn't really fit
<ktemkin> ~~sphinxcontrib-choose-your-own-archventure~~
<whitequark> heh
<hell__> nice :)
<hell__> "sphinxcontrib-platform-specific"?
<ktemkin> platform-tabs seems descriptivist enough
<hell__> ^ sounds good
* hell__ is bad at naming things
<awygle> ok back
<awygle> i like platform-tabs but platform-tabs does lock you into one presentation (tabs)
<whitequark> what other presentations can there be?
<awygle> i was just asking myself that question and all that came up were phone-style expandable sections, which probably don't fit this use case
<awygle> so tabs is probably fine
<whitequark> mk alright
<whitequark> now the question i actually wanted to ask you
<whitequark> first, do you have any time for nmigen soon?
<awygle> yes
<awygle> i have a 3-day nmigen-only weekend in fact
<FL4SHK> awygle: any chance you can update nmigen-boards?
<awygle> just have to survive till ~5pm today
<awygle> FL4SHK: i can, or you could
<awygle> i don't actually have push authority so it'd go through wq regardless
<whitequark> FL4SHK: what should I change?
<awygle> whitequark: i'm assuming there was a "second"?
<whitequark> awygle: oh, yeah
<whitequark> what do you think about #355?
<awygle> i thought we agreed on that already
<awygle> as_value, no eq except for things that are built in (e.g. record)
<whitequark> oh i mean about implementing it
<awygle> oh
<awygle> sure
<whitequark> we also need a new name for it
<whitequark> CustomValue?
<FL4SHK> whitequark: DE0-CV's SDRAM doesn't work
<whitequark> something like that, it's not just user
<whitequark> FL4SHK: sure. do you have a patch?
<awygle> oh, do we? i didn't have an issue with UserValue, but CustomValue is also fine
<whitequark> awygle: it's going to be used internally too, like for records and streams
<awygle> fair point
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<FL4SHK> whitequark: how do I make the patch?
<awygle> ok i'll implement #355 then, shooting for doing it this evening (after 5pm local, it currently being almost 1pm)
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<whitequark> FL4SHK: do you know how to use github?
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<_whitenotifier-b> [nmigen] alanvgreen opened pull request #420: Update license and copyright info - https://git.io/JJTYQ
<_whitenotifier-b> [nmigen] codecov[bot] commented on pull request #420: Update license and copyright info - https://git.io/JJTYN
<_whitenotifier-b> [nmigen] codecov[bot] edited a comment on pull request #420: Update license and copyright info - https://git.io/JJTYN
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<_whitenotifier-b> [nmigen] whitequark reviewed pull request #420 commit - https://git.io/JJT3G
<_whitenotifier-b> [nmigen] whitequark reviewed pull request #420 commit - https://git.io/JJT3Z
<_whitenotifier-b> [nmigen] whitequark reviewed pull request #420 commit - https://git.io/JJT3n
<whitequark> jeanthom: here?
<_whitenotifier-b> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JJTsv
<_whitenotifier-b> [nmigen/nmigen] whitequark 8dd28fe - compat.fhdl.specials: fix handling of tristate (i=None) pins.
<_whitenotifier-b> [nmigen] whitequark closed issue #406: Can't instantiate a Tristate without input - https://git.io/JfdWq
<whitequark> FL4SHK: anyway, if you know how to send a github PR, feel free; if you don't, you can just email me a patch, or put it on paste.debian.net or something
<_whitenotifier-b> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±12] https://git.io/JJTsf
<_whitenotifier-b> [nmigen/nmigen] whitequark 554cc50 - Deploying to gh-pages from @ 8dd28fecc6348474d61d57fda5eedfbb78cdb7e9 🚀
<_whitenotifier-b> [nmigen] whitequark commented on issue #24: Updated user guide introduction for nmigen. - https://git.io/JJTs3
<_whitenotifier-b> [nmigen] whitequark closed issue #24: Updated user guide introduction for nmigen. - https://git.io/JJTss
<ktemkin> gravejac: as I mentioned on Discord, whitequark has some simple code-poking changes I thought you could help with
<ktemkin> whitequark: meet Jacob; one of the engineers I manage at GSG
<whitequark> hi Jacob!
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<_whitenotifier-b> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±3] https://git.io/JJTGE
<_whitenotifier-b> [nmigen/nmigen] whitequark dcbcc2f - test: remove FHDLTestCase.assertRaisesRegex.
<_whitenotifier-b> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±12] https://git.io/JJTGV
<_whitenotifier-b> [nmigen/nmigen] whitequark cbee3c2 - Deploying to gh-pages from @ dcbcc2f176a84dee6b0773e226e309ea66017981 🚀
<_whitenotifier-b> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±3] https://git.io/JJTG6
<_whitenotifier-b> [nmigen/nmigen] whitequark fd5ee54 - test: remove FHDLTestCase.assertRaisesRegex.
<_whitenotifier-b> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±10] https://git.io/JJTGD
<_whitenotifier-b> [nmigen/nmigen] whitequark 85ba498 - Deploying to gh-pages from @ fd5ee548b6e333c92877440524c116e09bdd7c73 🚀
<whitequark> gravejac: so the first thing I wanted to ask you to do is to fix a longstanding issue with nMigen tests, stemming from my misunderstanding of the documentation
<gravejac> Hello!
<whitequark> where assertRaises() has an argument "msg" but it doesn't mean that there's a check that the exception's message matches "msg"; instead it's the message displayed when the assertion fails, which isn't very useful
<gravejac> That sounds good
<whitequark> the fix is really to use assertRaisesRegex instead of assertRaises, which takes the exception class and the message *regex*
<whitequark> we have around two hundred assertRaises and assertWarns invocations which need to be changed to use the *Regex variants
<whitequark> it's probably going to take longer to automate it than to do it manually
<whitequark> so, that's what I'd like to ask you do: this replacement, basically https://paste.debian.net/1154892/
<whitequark> er, sorry, wrong paste
<whitequark> the messages should all have ^$ and have regex special characters escaped
<whitequark> sounds good?
<gravejac> Sorry, back. But yes sounds good!
<whitequark> ok, great
<_whitenotifier-b> [nmigen/nmigen] whitequark pushed 2 commits to master [+0/-0/±2] https://git.io/JJTnl
<_whitenotifier-b> [nmigen/nmigen] whitequark 76b3ef4 - docs/index: rename to "Language & toolchain".
<_whitenotifier-b> [nmigen/nmigen] whitequark f24f1b0 - docs/lang: document constshifts.
<Falteckz> Surprised that it isnt a simple regex to regex that regex.
<_whitenotifier-b> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±17] https://git.io/JJTnB
<_whitenotifier-b> [nmigen/nmigen] whitequark 419fb31 - Deploying to gh-pages from @ f24f1b02e871d8c7af9ead26c615645ccfcb0016 🚀
<whitequark> i mean i don't care how it's done as long as i'm not the one who has to come up with it and verify that it works...
<_whitenotifier-b> [nmigen] whitequark commented on issue #378: Add shift left/right by constant amount - https://git.io/JJTnu
<_whitenotifier-b> [nmigen] whitequark commented on issue #355: [RFC] Redesign UserValue to avoid breaking code that inherits from it - https://git.io/JJTnK