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<whitequark>
TD-Linux: should be usable
<whitequark>
please file any issues as bugs
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<MadHacke1>
whitequark: Is there a sane way to do a switch on multiple signals at once? e.g. Cat(cycle, phase, addressing_mode)? I tried with a Cat() and a simple tuple but got errors on either the Switch or the Case for each situation.
MadHacke1 is now known as MadHacker
<MadHacker>
with m.Switch(Cat(self.cycle, self.phase, self.instr_addr_mode))
<MadHacker>
Oops, but yeah, that.
<whitequark>
basically no
<whitequark>
it might be conceivable to turn m.Switch into a pattern matching construct
<whitequark>
but that would be in the medium term future
<MadHacker>
Thanks; I'll come up with some situation-specific syntactic sugar for myself for now.
<MadHacker>
I guess the only real problem doing it by just collapsing them all into one integer/bitmask/string is that you don't necessarily know all the widths?
<whitequark>
what I want to do is to be able to compositionally add syntax to Module
<whitequark>
so you could build it yourself if you wanted
<whitequark>
unfortunately that's kinda really hard
<whitequark>
yes.
<whitequark>
in boneless I did a hack like that but it's ugly
<MadHacker>
How smart is whatever comes after? i.e. if I just expand out each Case with a Cat parameter into a little set of nested switches (which basically means lots of switches with the same input will get generated), will badness ensue?
<MadHacker>
with m.Switch(Cat(A,B)): with m.Case(Cat(1,0)): blah -> with m.Switch(A): with m.Case(1): with m.Switch(B): with m.Case(0): blah
<MadHacker>
Obviously can't have a condition that splits across the boundary between elements with that arrangement but that doesn't matter for my scenario.
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<whitequark>
that is an excellent question
<whitequark>
you should try it and see
<MadHacker>
Will do.
<whitequark>
I would expect the main problem come from the column order selection in processes
<whitequark>
but that's speculation
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* zignig
has managed to get a Boneless-V3 working in cxxrtl, now for an interface.
<MadHacker>
Yak-shaving here; the short answer to my question about switch/case above is that the resulting verilog matches the python pretty much like-for-like, but what consequence that has in the generated output I don't know, because I'm in the middle of rebuilding yosys because SGSR isn't in 0.9 and I'm building for ECP5 and...
<MadHacker>
<creates more bald yaks>
<whitequark>
the ECP5+Yosys flow doesn't go through Verilog
<whitequark>
but yes
<whitequark>
the semantics is the same
<MadHacker>
Well, I generated verilog to look at, and then didn't have a good feel for how that would affect actual FPGA output, so I was building for ECP5.
<MadHacker>
It's honestly what I expected but I wanted to test rather than assume.
<_whitenotifier-f>
[nmigen-boards] whitequark commented on pull request #64: resources: distinguish "dte"/"dce" roles of UARTResource - https://git.io/JfyuS
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<shizoor>
Hi, is there a place to check known bugs before I ask and look silly?
<shizoor>
I've made a circuit for driving a VGA monitor and displaying raster bars, and if I use if statements to create the clock, it works, but if I use modulo it behaves oddly.
<shizoor>
with m.If(self.v_timer == 0 ):m.d.sync += self.h_timer.eq(0)
<shizoor>
with m.Else():m.d.sync += (self.h_timer.eq(0))
<shizoor>
#m.d.comb += self.h_timer.eq(self.v_timer%386) # This doesn't work
<shizoor>
with m.Elif(self.h_timer < 386):m.d.sync += self.h_timer.eq(self.h_timer+1) #this does ask why.
<whitequark>
er
<whitequark>
ok, tpw_rules is probably right here
<whitequark>
do you meet timing?
<shizoor>
Do you mean does it meet VGA spec?
<whitequark>
can you upload your entire project somewhere? it'd be easier that way
<shizoor>
It doesn't meet spec but the second method gets me a picture. First one gets me what looks like a picture with some H sync pulses missing.
<tpw_rules>
your synthesis tool should give a warning if it doesn't think your logic can run at the clock rate you're giving it
<whitequark>
how are you generating h pulses exactly?
<shizoor>
Sure, I'll put it on livejournal (sorry, behind China's digital iron curtain)
<whitequark>
tpw_rules: it should be a hard error in nextpnr these days
<MadHacker>
shizoor: Using % means you're generating a divider in the resulting logic. A divider is a big slow thing, to the point where it may not even run at the VGA pixel clock. You probably just want to subtract off 386 each time it's above that or something.
<MadHacker>
Doing it with % works in software but is usually a bad idea in hardware.
<tpw_rules>
yeah it is in nextpnr, but it's definitely not in quartus or ISE
<shizoor>
@MadHacker That makes sense. Like it's still busy dividing when the monitor is expecting a pulse?
<MadHacker>
Yep.
<tpw_rules>
in quartus it's a "critical warning" which i find to be an interesting concept
<whitequark>
in vivado too iirc
<shizoor>
I'll upload so people can take a look at my mess anyway. :)
<shizoor>
It's weird because it "sorts itself out" half way through the vertical scan. Other frequencies produce other odd effects like it stopping and starting. I could see how a delay might be intermittant.
<shizoor>
@whitequark The sync pulses are made using "with m.If" statements referring to the h_timer or v_timer to see how far through the scan it is, same with porches. I couldn't get gtkwave to look at an entire scan. I think I know what to avoid now. This has helped a lot.
<shizoor>
File "/usr/lib/python3.8/subprocess.py", line 364, in check_call
<shizoor>
raise CalledProcessError(retcode, cmd)
<shizoor>
subprocess.CalledProcessError: Command '['sh', 'build_top.sh']' returned non-zero exit status 1.
<whitequark>
ohhhh I see what happened
<shizoor>
I get that when I have two things in "sync" that disagree with eachother, I think.
<whitequark>
shizoor: ok so here's the missing piece of the puzzle
<whitequark>
normally, nextpnr makes sure that your code runs fast enough to work at the required clock
<whitequark>
but if you do something like `h_sync = h_timer % 384 > 341`, then nextpnr doesn't know what there are timing restrictions on h_sync!
<shizoor>
ok.
<whitequark>
here is a general advice: don't use combinatorial signals to drive FPGA pins
<shizoor>
Ok.
<whitequark>
or rather, don't assign combinatorial expressions to FPGA pins
<whitequark>
the reason is that there is no guarantee that the combinatorial functions in an FPGA are glitchless
<whitequark>
i.e. there can be some time until even something simple like a&b settles on a value after a or b change
<shizoor>
Ah I see. Yes, I've been seeing some interesting psychadelia this end.
<whitequark>
if you explicitly register the signal via m.d.sync then this won't happen
<whitequark>
for your circuit it probably doesn't matter, but for more complex ones, it is worth looking into IO buffer registers
<whitequark>
to make sure the phase of the output does not change related to FPGA clock from one PNR run to another
<shizoor>
Thanks. The vgapins object I create is all combinatorial : m.d.comb += self.red0.o.eq(self.x[0])
<shizoor>
m.d.comb += self.red1.o.eq(self.x[1])
<shizoor>
m.d.comb += self.red2.o.eq(self.x[2])
<shizoor>
etc, Change all that to sync? Would it build then?
<Lofty>
Yes
<shizoor>
Slowly starting to understand this. :)
<shizoor>
Thanks!
<Lofty>
It's a bit tricky to know what should and should not be combinational
<Lofty>
If you register too much logic you might use the LUTs inefficiently
<Lofty>
If you don't register enough, you fail timing
<shizoor>
Now it's becomeing clearer. I've put everything in sync that drives pins. If I use modulo, ERROR: Max frequency for clock 'cd_sync_clk1_0__i': 6.45 MHz (FAIL at 12.00 MHz), if I use if statements, it builds. It runs and the picture is looking nice. Thanks!
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<_whitenotifier-f>
[nmigen-boards] igrr commented on pull request #64: resources: distinguish "dte"/"dce" roles of UARTResource - https://git.io/JfyKq
<_whitenotifier-f>
[nmigen-boards] igrr edited pull request #65: Add role to UARTResouce and fix UART flow control pin inconsistencies - https://git.io/JfDxq
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<mithro>
whitequark: I wonder if you can steal them for nmigen? :-P
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<whitequark>
maybe? it's hard to scale renderings like that, they work better for docs and demos i think
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<_whitenotifier-f>
[nmigen-boards] whitequark commented on pull request #65: Add role to UARTResouce and fix UART flow control pin inconsistencies - https://git.io/JfyiP
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<_whitenotifier-f>
[nmigen] andresdemski opened issue #402: Consider slice as signal in Record initialization - https://git.io/JfyX5
<_whitenotifier-f>
[nmigen] andresdemski edited issue #402: Consider slice as signal in Record initialization - https://git.io/JfyX5
<_whitenotifier-f>
[nmigen] whitequark commented on issue #402: Consider slice as signal in Record initialization - https://git.io/Jfy1k
<_whitenotifier-f>
[nmigen] andresdemski commented on issue #402: Consider slice as signal in Record initialization - https://git.io/Jfy1l
<_whitenotifier-f>
[nmigen] whitequark commented on issue #402: Consider slice as signal in Record initialization - https://git.io/Jfy1y
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<_whitenotifier-f>
[nmigen] andresdemski commented on issue #402: Consider slice as signal in Record initialization - https://git.io/JfyM0
<_whitenotifier-f>
[nmigen] whitequark commented on issue #402: Consider slice as signal in Record initialization - https://git.io/JfyMV