ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at · logs at
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<Sarayan> Do arrays of signals exist? As in I want say 7 16-bits Signals, but I'm not talking about a memory with 7 entries, I'll address them individually
<Sarayan> There's of course self.ah = [ Signa(16), Signa(16), ... ] but I suspect it kinda fucks everything up internally, doesn't it?
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<whitequark> you can use Array([Signal(16), Signal(16), ...])
<Sarayan> won't it make a mess of signal naming?
<whitequark> Array([Signal(16, name=f"ah_{n}") for n in range(16)])
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<awygle> why no f-strings in nmigen? :p
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* cr1901_modern is in way too many damn channels and autojoin doesn't work properly...
<cr1901_modern> _florent_: Just out of curiosity, has there been movement to convert litex from omigen to the compat layer (or even nmigen)?
<whitequark> awygle: 3.6
<whitequark> wait, no
<whitequark> 3.6 has f-strings
<whitequark> what it does not have is format specifiers for f-strings
<whitequark> so you're stuck doing manual conversion, which is worse than just using .format()
<awygle> mmm
<awygle> didn't we move off 3.6 recently because we got rid of like, bitarray or something?
<awygle> might be thinking of glasgow, or just wrong entirely
<whitequark> nmigen supports 3.6 as basically matter of policy
<whitequark> glasgow does not because it has a much smaller audience
<awygle> ah
<awygle> well i don't actually care, i was just curious when i saw you use one in the above code sample
<awygle> the nice thing about python is that you have so many options for string formatting (/s)
<whitequark> f-strings are ok
<awygle> I like them the most, yeah
<awygle> I wish rust had them
<Lofty> whitequark: out of curiosity, do you consider raising the minimum Python version a breaking change?
<agg> awygle: right? it's annoying that rust has python-esque format with {} but no actual string interpolation/f-strings
<agg> it seems like it would be totally doable with basically the same macro
<awygle> It can be done as a proc macro. I wrote it, so did somebody else. I am waiting on stable proc macros in expression position to start actually using it.
<agg> sure, I just wish it was how println and friends always worked
<agg> format!("hello {name}", name=name) is sooo close
<awygle> Agreed
<agg> ah, nice
<awygle> Would it be a backwards incompatible change if it did work that way?
<agg> though unfortunate overlap with heh
<awygle> Mine is called `formata` lol
<agg> I'm not sure, it seems like it could be done in a back-compat way maybe?
<awygle> Yeah it does. We should write an rfc :-P
<agg> i'm surprised no one has already...
<awygle> They have
<awygle> And it was accepted
<agg> ooh. though just for single variable names rather than expressions
<awygle> Tracking issue is still open tho. Guess people have had better things to do since January
<agg> not clear to me if that supports format specifiers, the rfc seems to be mostly for printing strings
<agg> but I want like "the result is {x:05d}"
<agg> I expect it probably would work and just isn't said explicitly in the rfc. well, that's something to look forward to.
<awygle> format_args already supports those, the way this is phrased I'd expect to get that for free
<whitequark> Lofty: "depends"
<whitequark> no one actually follows the letter of semver so whether something is a breaking change according to its spirit is basically an arbitrary choice
<whitequark> for example, suppose we shipped a few releases which accidentally required 3.7 and no one noticed because everyone moved to 3.7
<whitequark> i'd have a hard time calling that a "breaking change" because it didn't actually break any code people care about!
<whitequark> but that's the philosophical view
<whitequark> the practical view is that people will almost certainly complain about raising minimum python version, so yeah, it's almost certainly breaking
<whitequark> it can go through a deprecation cycle like everything else we have, for example
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<awygle> i agree with that position fwiw
<awygle> changing MS~R~PV should be considered breaking
<ananan> How can i pull in a verilog module into a project that's being built with nmigen
<ananan> is there any way to easily do so, or do i just need to have my top-level be verilog and use nmigen to generate verilog and build the whole project as verilog?
<awygle> you're looking for "Instance"
<ananan> ah
<ananan> how does it know where to find the verilog / systemverilog file?
<Lofty> It doesn't
<Lofty> That's up to the compiler
<Lofty> Though I think there's a way to include files within a platform
<Lofty> I can't remember how though
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<ananan> Instance doesnt seem to be doing anything at all
<ananan> no warnings no errors
<Lofty> Look at the generated code
<ananan> it doesnt appear to be picking it up
<ananan> even if i put a nonexistent module name
<Lofty> Can I see your usage of Instance?
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<ananan> `verilog_boi = Instance("vblink", i_clk=clk_in, o_led=blinky_out)`
<ananan> theres a module named vblink in a file in the same directory as the python file thats calling this
<Lofty> And what do you expect to happen?
<Lofty> I think you need to add it to the platform
<ananan> well should cause the signal connected to o_led to turn on and off
<ananan> oh where do i do that?
<Lofty> whitequark: ^
<miek> there's some discussion on it here:;
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<awygle> you need to add the file to the platform
<awygle> miek linked exactly what i was gonna link so nvm i am not needed here lol
<awygle> ananan: see above
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