ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen
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<zignig> I am messing around with cxxrtl and I am trying to extract the current value from a debug_item.
<zignig> how do you get the current calue of the wire from a debug_item construct ?
<zignig> *value
<whitequark> item->curr
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<zignig> hmmm , not a pointer.
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<whitequark> item.curr, sure
<_whitenotifier-f> [nmigen-boards] whitequark closed issue #63: UARTResource flow control signals direction mismatch for ICEStickPlatform - https://git.io/JfDBE
<_whitenotifier-f> [nmigen-boards] whitequark closed pull request #65: Add role to UARTResouce and fix UART flow control pin inconsistencies - https://git.io/JfDxq
<_whitenotifier-f> [nmigen/nmigen-boards] whitequark pushed 7 commits to master [+0/-0/±7] https://git.io/Jf9RV
<_whitenotifier-f> [nmigen/nmigen-boards] igrr 5d56f7f - [breaking-change] resources: distinguish "dte"/"dce" roles of UART.
<_whitenotifier-f> [nmigen/nmigen-boards] igrr f1aeee1 - blackice_ii: fix UART RTS/CTS direction.
<_whitenotifier-f> [nmigen/nmigen-boards] igrr 1acda44 - [breaking-change] blackice: remove UART RTS/CTS signals.
<_whitenotifier-f> [nmigen/nmigen-boards] ... and 4 more commits.
<_whitenotifier-f> [nmigen-boards] whitequark commented on pull request #65: Add role to UARTResouce and fix UART flow control pin inconsistencies - https://git.io/Jf9Rw
<jeanthom> Hi! Is there an easy way to check if NMIGEN_verbose is set in an Elaboratable?
<Lofty> Use the Python environment tools
<Lofty> e.g. os.environ["NMIGEN_verbose"]
<whitequark> why do you want to check it?
<jeanthom> Lofty, yep that seems the best option but I was curious if there was a more idiomatic way of doing it
<jeanthom> whitequark, I want to add some debug information into some elaboratables. Say I want to encapsulate a PLL and calculate automatically its parameters, with NMIGEN_verbose=1 it would display its parameters, estimated output frequency, etc.
<whitequark> I would suggest you go for the Python logging module
<whitequark> the NMIGEN_verbose option is doing something different
<whitequark> namely, it affects how the build scripts are generated, not how Python code runs
<whitequark> of course, you can alwasys pass verbose="1" to the build() function based on your own parameter
<jeanthom> Ok, I thought it was meant as a general verbose switch that would activate logging everywhere
<whitequark> nope.
<_whitenotifier-f> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/Jf9uJ
<_whitenotifier-f> [nmigen/nmigen] whitequark 133d4f4 - back.verilog: remove unused imports. NFC.
<_whitenotifier-f> [nmigen/nmigen] whitequark pushed 3 commits to master [+1/-0/±4] https://git.io/Jf9gN
<_whitenotifier-f> [nmigen/nmigen] whitequark a7b8ced - nmigen.cli: fix file type autodetection code.
<_whitenotifier-f> [nmigen/nmigen] whitequark bddec37 - _yosys: translate Yosys warnings to Python warnings.
<_whitenotifier-f> [nmigen/nmigen] whitequark 545e49c - back.cxxrtl: new backend.
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<_whitenotifier-f> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/Jf92O
<_whitenotifier-f> [nmigen/nmigen] whitequark 44fbf87 - test: fix example test after commit a7b8ced9.
<_whitenotifier-f> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/Jf92c
<_whitenotifier-f> [nmigen/nmigen] whitequark ca36091 - test: fix example test after commit a7b8ced9.
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