<_whitenotifier-f>
[nmigen-boards] trabucayre opened pull request #67: tinyfpga_axN: use lattice_machxo_2_3l instead of lattice_machxo2 - https://git.io/JfNqO
<FL4SHK>
I've installed nmigen and nmigen-boards on Arch Linux
<FL4SHK>
ah, I don't have pyvcd installed
<FL4SHK>
any way to do multiple Verilog modules?
<FL4SHK>
also, getting an error upon trying to program the dev board
<FL4SHK>
"Can't scan JTAG chain. Error code 89."
<FL4SHK>
I'll try rebooting my machine and see if that works
<FL4SHK>
well, that doesn't seem to have worked.
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<FL4SHK>
next guess: need udev rules
<FL4SHK>
that fixed it
<FL4SHK>
additional question: any way to use a PLL with nmigen (without having to boot up a Quartus project)
<Lofty>
FL4SHK: Instance an altera_pll
<tpw_rules>
you still need quartus to calculate the parameters
<tpw_rules>
last time i wanted to do that at least
<FL4SHK>
Lofty: how do I instance a module in nmigen?
<FL4SHK>
does that work for instancing another elaboratable?
<tpw_rules>
FL4SHK: it's called an Instance
<tpw_rules>
and no it's not for instancing other elaboratables
<tpw_rules>
if you have a module that's instantiated in verilog like the_module #(SOME_PARAM = 69) cool_name (.some_output(signal_a), .some_input(signal_b));
<tpw_rules>
then you would write it in nmigen as cool_name = Instance("the_module", p_SOME_PARAM=69, o_some_output=signal_a, i_some_input=signal_b)
<tpw_rules>
honestly i would just make a PLL megafunction with quartus that's set to your desired output and then just instantiate the resulting module
<whitequark>
FL4SHK: is there a reason you're not using pip?
<FL4SHK>
whitequark: pip?
<FL4SHK>
No, there's not
<FL4SHK>
tpw_rules: what if I want to instantiate an elaboratable?
<tpw_rules>
then just construct it
<FL4SHK>
Oh? Okay.
<FL4SHK>
even if there's an `elaborate` function? Does nMigen handle calling that automatically?
<FL4SHK>
also, regarding the pll, will nMigen's board things handle the sdc stuff?
<FL4SHK>
I honestly might want to just synthesize to Verilog with nMigen and use a Quartus project...
<whitequark>
you can add a clock constraint on the PLL output with `platform.add_clock_constranit(out_clk, freq)`
<FL4SHK>
that sounds great
<FL4SHK>
looks like "altpll" is grayed out
<FL4SHK>
seems I might be looking for something else
<FL4SHK>
that's really strange
<FL4SHK>
I thought I'd be able to use a PLL...
<tpw_rules>
do you have a device selected?
<FL4SHK>
yeah
<FL4SHK>
"Megafunction altpll is not supported by the selected device family (Cyclone V)"
<FL4SHK>
oh, I must need Altera_PLL
<FL4SHK>
seems I don't *have* that
<FL4SHK>
there we go
<FL4SHK>
had to get it from the IP catalog
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<Lofty>
I did say altera_pll explicitly :P
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<awygle>
Hi FL4SHK
<awygle>
whitequark: I'm out of town this weekend, very asynchronous
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<whitequark>
awygle: so it turns out "wasp" and "waspy" are taken
<FL4SHK>
so I have a little question about `Subsignal`s within a `Resource`
<FL4SHK>
I've got a `Resource` called "vga" and a `Subsignal` called "r"
<FL4SHK>
can I access this via `platform.request("vga.r", ...)`?
<whitequark>
nope; you can only do `vga = platform.request("vga"); vga.r`
<_whitenotifier-f>
[nmigen] colepoirier commented on issue #407: AttributeError: module 'importlib.resources' has no attribute 'files' - https://git.io/JfNob
<_whitenotifier-f>
[nmigen] whitequark commented on issue #407: AttributeError: module 'importlib.resources' has no attribute 'files' - https://git.io/JfNKc
<_whitenotifier-f>
[nmigen] colepoirier commented on issue #407: AttributeError: module 'importlib.resources' has no attribute 'files' - https://git.io/JfNKi
<_whitenotifier-f>
[nmigen] whitequark commented on issue #407: AttributeError: module 'importlib.resources' has no attribute 'files' - https://git.io/JfNK9
<_whitenotifier-f>
[nmigen] whitequark edited a comment on issue #407: AttributeError: module 'importlib.resources' has no attribute 'files' - https://git.io/JfNK9
<_whitenotifier-f>
[nmigen] colepoirier commented on issue #407: AttributeError: module 'importlib.resources' has no attribute 'files' - https://git.io/JfNKd
<_whitenotifier-f>
[nmigen/nmigen-yosys] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JfNKj
<_whitenotifier-f>
[nmigen/nmigen-yosys] whitequark db4407f - [skip ci] Remove the installed shared directory before copying over.
<_whitenotifier-f>
[nmigen] whitequark commented on issue #407: AttributeError: module 'importlib.resources' has no attribute 'files' - https://git.io/JfN6T