<whitequark>
jeanthom: ping me once you're online please
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<_whitenotifier-f>
[nmigen-soc] jfng commented on issue #18: Wishbone access from initiator bus with data_width smaller than the one of the subordinate bus. - https://git.io/Jfham
<_whitenotifier-f>
[nmigen-soc] whitequark commented on issue #18: Wishbone access from initiator bus with data_width smaller than the one of the subordinate bus. - https://git.io/Jfhas
<tpw_rules>
jeanthom: "[01:50] whitequark]jeanthom: ping me once you're online please"
<jeanthom>
tpw_rules, thx!
<jeanthom>
whitequark, i'm here!
<whitequark>
jeanthom: so I talked to key2 and he educated me about DDR
<whitequark>
nmigen-boards is currently just wrong
<whitequark>
and you are right, it needs to be changed
<whitequark>
specifically dq should be split into groups of 8 that are independently controlled
<whitequark>
afaiu
<whitequark>
does this match your understanding?
<jeanthom>
whitequark, by "independently controlled" you mean that you are able to change the direction for a specific pin or for the whole group?
<whitequark>
you are only ever able to change direction for an entire Subsignal
<whitequark>
but since DDR uses 8-wide chunks, it is OK to have subsignals that are also 8-wide
<jeanthom>
In LiteDRAM, _florent_ declares a TSHX2DQSA (OE signal generation) instance for each pin
<whitequark>
sure
<whitequark>
change that
<whitequark>
or is there a reason it's a bad idea to change it?
<jeanthom>
That the question :/
<daveshah>
Well atm nextpnr won't duplicate them automatically
<whitequark>
okay, I guess I'm going to have to figure this out myself
<jeanthom>
I can't information from Lattice saying that you absolutely should for routing reasons
<whitequark>
hmm
<daveshah>
I don't know if Diamond does
<jeanthom>
*can't find
<daveshah>
I don't know if Vivado duplicates the tristate serdes automatically, either
<whitequark>
okay, I see the problem
<whitequark>
I'm not sure offhand what to do with it, I'll think about it
<whitequark>
I suspect the solution might be to avoid messing with the platform layer altogether and instead add a way to instantiate something in the toplevel module
<whitequark>
but... right now that would work really badly due to some unrelated bugs
<whitequark>
I'll need to think about the best solution here
<whitequark>
jeanthom: can you open an issue to track this?
<jeanthom>
whitequark, sure
<whitequark>
thanks
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<_whitenotifier-f>
[nmigen] jeanthom opened issue #413: Per-pin direction control for platform defined IOs - https://git.io/JfhbD
<_whitenotifier-f>
[nmigen] whitequark commented on issue #413: Per-pin direction control for platform defined IOs - https://git.io/JfhNe
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<_whitenotifier-f>
[nmigen] jeanthom commented on issue #413: Per-pin direction control for platform defined IOs - https://git.io/JfhAn
<_whitenotifier-f>
[nmigen] whitequark commented on issue #413: Per-pin direction control for platform defined IOs - https://git.io/JfhAD
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<_whitenotifier-f>
[nmigen] jeanthom commented on issue #413: Per-pin direction control for platform defined IOs - https://git.io/JfjeI
<_whitenotifier-f>
[nmigen] whitequark commented on issue #413: Per-pin direction control for platform defined IOs - https://git.io/JfjeO
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<esden>
For anyone interested, I will be fumbling my way through nmigen on stream in about half an hour or so. If nothing I will just make a fool of myself. :D https://www.twitch.tv/esden
<whitequark>
oh neat
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<FL4SHK>
whitequark: have a little issue
<FL4SHK>
all the ports of a module are inside of a record
<FL4SHK>
I tried just placing the record as the ports
<FL4SHK>
but it didn't work
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<mithro>
I just got a nice email from Xilinx -- "The request for the Xilinx Unisim Library to be published as open source has been hosted on GitHub with the Apache 2.0 license here: https://github.com/Xilinx/XilinxUnisimLibrary -- The repo is marked as ‘archived’, but it obviously can be forked for further development by the community. "