<Sarayan>
hmmm, the C++ api seems to be missing a thing or two
<whitequark>
like what?
<Sarayan>
like I want to lookup an item at startup for fast access during the sim, how do I do that?
<whitequark>
you call `debug_info` once, it builds a map for you, you look up in that map
<whitequark>
the references are valid for the lifetime of the design
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<Sarayan>
ok
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<Sarayan>
so design.debug_info(items); clk = items["i_clk"].data; and use *clk ?
<whitequark>
correct
<Sarayan>
ok, simple enough
<whitequark>
yep, simple is what i'm aiming for
<whitequark>
c++ has more than enough bullshit for me to add more
<Sarayan>
and I can get memories, I can recurse, I can enumerate if I'm not sure of a name
<Sarayan>
That's going to make my life significantly nicer
<Sarayan>
I really like it
<whitequark>
:)
<Sarayan>
up to now I had to push up internal signals into the main module interface to be able to look at them
<Sarayan>
that was not pleasant
<whitequark>
wait
<Sarayan>
I'm sure it was possible to find them somewhere
<Sarayan>
I just had no clue how
<whitequark>
the debug interface doesn't make it any easier
<Sarayan>
and the names were "interesting"
<whitequark>
instead of items["\\submod \\i_clk"] you can always use top.p_submod.p_i__clk
<Sarayan>
even after flatten?
<whitequark>
ohh
<whitequark>
ok so the flattening is a bit tricky
<Sarayan>
I mean at the start of cxxrtl flatten was required
<whitequark>
let me rebase that branch so you can actually use non-flattened names
<whitequark>
yes
<whitequark>
you still want it for performance
<whitequark>
hang on
* Sarayan
goes grab a coke :-)
<whitequark>
okay, rebased, *now* you can use original names even in flattened designs
<Sarayan>
neat
<Sarayan>
finding the correct variable name in flattened designs was a little too much :-)
<whitequark>
yeah, that's fair, I momentarily forgot about that
<Sarayan>
one can't think of everything
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<agg>
i'm rebuilding an old design with new nmigen and getting "nmigen.hdl.cd.DomainError: Signal (rst io) refers to reset of reset-less domain 'io'", but the traceback is all nmigen internals from build(), so I can't figure out where the errant signal is actually coming from
<agg>
is there any way to work out what module that signal is being defined in or anything like that?
<agg>
a binary search of deleting things suggests it might be to do with asyncfifo, hmm
<agg>
further deletions suggest one AsyncFIFO is causing the problem and a second AsyncFIFO with the clock domains the other way around is fine, even though both domains in question are reset_less, hmmm
<agg>
i know asyncfifo had a few changes since this last build (e.g. i was using din and dout and readable and we and re signals, which are now r_data/r_rdy/etc)
<agg>
but afaict AsyncFIFO uses w_rst=ResetSignal(...., allow_reset_less=True)
<agg>
hmm, I think what's happening is: I have a domain "x" which is reset_less, I have a module Foo containing AsyncFIFO(w_domain="y"), and I do DomainRenamer({"y": "x"})(Foo()) in my top level
<agg>
and somehow y getting renamed to x is causing the asyncfifo to still want an actual reset signal?
<agg>
the other AsyncFIFO has w_domain=sync which is also reset_less but doesn't get renamed
<agg>
so maybe ResetSignal(allow_reset_less=True) breaks with domains which aren't defined at all but are later renamed to reset_less signals?
<_whitenotifier-f>
[nmigen] adamgreig opened issue #400: ResetSignal's allow_reset_less fails on renamed reset_less domains - https://git.io/Jf1zx
<_whitenotifier-f>
[nmigen] adamgreig opened pull request #401: Preserve allow_reset_less when remapping ResetSignal. Closes #400 - https://git.io/Jf1g4
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<_whitenotifier-f>
[nmigen] codecov[bot] commented on pull request #401: Preserve allow_reset_less when remapping ResetSignal. Closes #400 - https://git.io/Jf1gp
<_whitenotifier-f>
[nmigen] codecov[bot] edited a comment on pull request #401: Preserve allow_reset_less when remapping ResetSignal. Closes #400 - https://git.io/Jf1gp
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<agg>
just checking i understand AsyncFIFO's fwft behaviour properly: after a single write, I expect to see valid r_data and r_rdy==1, and if I then blip r_en, r_rdy becomes 0 and r_data is no longer valid?
<agg>
so essentially r_rdy is more like "r_data valid" and r_en is like "acknowledge that i've seen the current data, go to the next entry if available"
<agg>
or in other words, r_data always shows me what's currently in the top of the queue, and r_rdy shows if the queue contains anything (in other words, if r_data is valid)
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<tpw_rules>
agg: yes
<tpw_rules>
then r_en acknowledges the top of the queue and the next entry is available on r_data the next cycle (if any)