ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen
<_whitenotifier-f> [nmigen] colepoirier opened issue #407: AttributeError: module 'importlib.resources' has no attribute 'files' - https://git.io/Jfb0J
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<_whitenotifier-f> [nmigen-boards] trabucayre opened pull request #66: Add Lattice MachXO3LF Starter Kit - https://git.io/Jfbon
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<_whitenotifier-f> [nmigen] whitequark commented on issue #407: AttributeError: module 'importlib.resources' has no attribute 'files' - https://git.io/Jfbyd
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<_whitenotifier-f> [nmigen-boards] whitequark commented on pull request #66: Add Lattice MachXO3LF Starter Kit - https://git.io/JfbH5
<_whitenotifier-f> [nmigen-boards] trabucayre commented on pull request #66: Add Lattice MachXO3LF Starter Kit - https://git.io/Jfb7w
<_whitenotifier-f> [nmigen-boards] whitequark commented on pull request #66: Add Lattice MachXO3LF Starter Kit - https://git.io/Jfb7d
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<FL4SHK> awygle: hello from IRC
<sorear> o/
<FL4SHK> oh hi sorear
<_whitenotifier-f> [nmigen-boards] trabucayre commented on pull request #66: Add Lattice MachXO3LF Starter Kit - https://git.io/Jfb5O
<FL4SHK> How do I use nmigen-boards?
<FL4SHK> oh cool, my dev board is supported
<ktemkin> FL4SHK: like you would any other python package; it just is a package that provides the various *Platform() classes
<_whitenotifier-f> [nmigen-boards] whitequark commented on pull request #66: Add Lattice MachXO3LF Starter Kit - https://git.io/JfbFL
<FL4SHK> ktemkin: thanks, I was mostly looking for "how do I use these classes"
<FL4SHK> looks like they call the synthesis tools directly
<FL4SHK> two of my dev boards (or maybe three, wasn't sure if the name was a complete match) are supported
<FL4SHK> I only have three dev boards
<whitequark> take a look at examples/board/
<whitequark> in the nmigen repository
<whitequark> awygle: have you looked at #369 since we last talked?
<whitequark> is there anything blocking you?
<whitequark> semi-related
<FL4SHK> whitequark: that solves it
<whitequark> I propose that we have meetings (virtual, on IRC) twice per month to coordinate what everything works on, so as to avoid a situation where an organization (or even individuals) using nMigen relies on something happening and it doesn't happen promptly because e.g. I don't even know that it's wanted
<whitequark> so for example, ktemkin could mention what GSG/LUNA needs, jfng could mention what LambdaConcept needs, someone from LibreSOC (I'm not sure who is on IRC from that project) what they need, and so on
<FL4SHK> Is there any way to simulate blocking assignments?
<FL4SHK> referring to `comb`
<whitequark> nope, very much by design; what do you need them for?
<FL4SHK> I use VHDL variables to compute temporary things sometimes
<FL4SHK> I suppose I can just use a separate signal...
<FL4SHK> there are times I write within-a-clock sequential code
<FL4SHK> For example, there was a long division implementation I did that computed one bit per clock cycle
<FL4SHK> but that algorithm wasn't really viable for setting up as a single expression
<FL4SHK> can nmigen do sequential code within a single clock?
<ktemkin> You can build intermediary logic trees store in regular python variables
<FL4SHK> That's what I'm looking for
<FL4SHK> I suppose I could include if statements in that by way of `Mux`
<ktemkin> if b and c are signals, a = (b & c) winds up storing essentially a logic netlist that’s (B AND C) in the python variable “a”
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<ktemkin> That gives you the Good Parts of what you can do with a VHDL non-blocking assignment
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<ktemkin> Er
<ktemkin> *blocking
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<ktemkin> for other things, you’d e.g. use an intermediary Signal as you’d use a non-blocking assignment in VHDL or a continuous assignment in Verilog
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<ktemkin> (that kind of dichotomy makes it clear how/when you’re building logic trees and avoids VHDL’s tendency to have complexity explosions when using blocking assignments)
<ktemkin> (sorry for my terseness, I’m IRC’ing from my cell phone as I wait for something)
<ktemkin> also, +1 to whitequark’s periodic meeting idea
<cr1901_modern> whitequark: When would the first meeting be? I'm interested in tailoring my SPI FV repo to nmigen, but I'm not available to at least July 3rd to work on, well, anything
<FL4SHK> ktemkin: IRCing from my cell phone is something I'd do if I had an SSH client set up on my phone
<FL4SHK> what you said makes sense
<FL4SHK> it didn't seem terse to me
<FL4SHK> new question about nmigen: anything like SV packed structs?
<FL4SHK> Those things are great.
<FL4SHK> I think I heard something about such a thing existing
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<FL4SHK> I can make do without such things
<FL4SHK> VHDL doesn't have them; it's just a nice feature to have
<FL4SHK> looks like records exist
<FL4SHK> I knew I had read that somewhere...
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<whitequark> cr1901_modern: I was thinking 1st and 15th of each month, or the next workday if it falls on a weekend
<whitequark> or a holiday etc
<ktemkin> whitequark: I find it often works better to do something like "1st and 3rd Monday"
<ktemkin> since a meeting on the 1st might conflict with one of my weekly meetings some months but not others
<whitequark> ah, let's do that instead
<anuejn> do you plan on doing irc meetings or some other plattform?
<whitequark> irc
<anuejn> ah nice :)
<whitequark> that seems to be the most accessible for everyone already participating
<whitequark> and no annoying zoom etc stuff
<anuejn> yup and has good logs & searchability
<whitequark> some rust teams use voice meetings, some rust teams do text, both seem to work reasonably well, so it's fine for us to choose whatever's most convenient in that regard
<whitequark> for the time: something like 1800 UTC, perhaps?
<whitequark> 1600 UTC might be less obnoxiously late for european folks
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<cr1901_modern> 1800 UTC is 2300 EST (sic)
<cr1901_modern> But fine... I can live w/ that
<ktemkin> eastern time?
<cr1901_modern> yes
<ktemkin> that'd be the other way around
<ktemkin> UTC minus 4
<ktemkin> 1800 UTC is 1400 EST, right?
<cr1901_modern> Yea, I can't add or subtract, don't mind me
<ktemkin> 1800 UTC is decent for me; 1600 UTC tends to be a bit early during non-DST hours here
ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · meetings each 1st & 3rd Monday at 1800 UTC
ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each 1st & 3rd Monday at 1800 UTC
<whitequark> so the next one will be at July 6th
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