ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen
<awygle> i _think_ you can do m.submodules.foo.memory? i'm not sure though
<awygle> i guess you've tried that though
<awygle> if that doesn't work i know for sure you can do the `self.memory_introspection_port` thing, but you'll want to do it in __init__() instead of elaborate()
<awygle> so that you can get at the handle to it when the object is constructed in the parent's elaborate()
<awygle> smkz: ^
<smkz> ah, so define the memory inside the __init__()?
<awygle> yeah
<awygle> that will work, there may be a more elegant way that i don't know though
<smkz> for something like "x = yield nine.submodules.msm.fsm_ready" in the process() function i get error "AttributeError: 'Cirno' object has no attribute 'submodules'" ;;
<smkz> i will try defining memory inside the __init__(); thanks!
<awygle> mm yeah that makes sense actually
<awygle> cuz you have a Cirno not a module
<smkz> i guess now that i have defined it inside the __init__ i can access it from the module above the one defining the memory
<smkz> but how would i thread it through that module so the one above *that* one can access it?
<smkz> uwaa
<smkz> apparently defining/instantiating that module inside the __init__; extracting the memory from it, and assigning it to the self.whatever did the trick
<awygle> nice!
<smkz> thank you for the help
<awygle> no problem, glad you got it working
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<whitequark> smkz: yeah at the moment you'll have to define the memory in __init__
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<_whitenotifier-c> [nmigen] rroohhh opened pull request #390: hdl.ast: fix typo - https://git.io/Jfahg
<_whitenotifier-c> [nmigen] codecov[bot] commented on pull request #390: hdl.ast: fix typo - https://git.io/Jfahx
<_whitenotifier-c> [nmigen] codecov[bot] edited a comment on pull request #390: hdl.ast: fix typo - https://git.io/Jfahx
<_whitenotifier-c> [nmigen] codecov[bot] edited a comment on pull request #390: hdl.ast: fix typo - https://git.io/Jfahx
<_whitenotifier-c> [nmigen] codecov[bot] edited a comment on pull request #390: hdl.ast: fix typo - https://git.io/Jfahx
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<_whitenotifier-c> [nmigen] whitequark closed pull request #390: hdl.ast: fix typo - https://git.io/Jfahg
<_whitenotifier-c> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JfVe8
<_whitenotifier-c> [nmigen/nmigen] rroohhh 26a15b3 - hdl.ast: fix typo
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<smkz> whitequark: thank you for the confirmation ^^;
<whitequark> it's one of fairly significant downsides at the moment
<whitequark> the worst part is FSMs actually
<whitequark> there is a hackish API for getting at the FSM state signal but i don't like it a lot
<whitequark> you have to do Fragment.get() on the root module and then use frag.get_generated() with the path to the FSM to grab its state
<whitequark> it's really not nice to use and I need to improve on it
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<awygle> i thought nmigen had a warning or something if you use a nonexistent clock domain
<awygle> but i can't seem to trigger it...
<awygle> maybe i need to be building instead of simulating or something
<awygle> i have now located the warning in question, but still not sure what causes it to happen, guess i'll just backtrace it...
<awygle> ah i was looking at the wrong thing all along, unsurprisingly