00:17 <whitequark> awygle: your stuff is fine actually, I'll just work with you on it until I can do post-commit review

00:18 <awygle> mk, if you say so. i know you're busy, don't wanna make it worse.

00:21 <cr1901_modern> awygle: https://github.com/cr1901/yosys-experiments/tree/master/clk2fflogic/tworegs

00:22 <cr1901_modern> >I'll probably fix this soon.

00:22 <cr1901_modern> Yea I should probably actually do that

00:22 <awygle> cool, thats what i expected it did. and do you know if sby's "multiclock on" is the same thing?

00:22 <cr1901_modern> yes, should be

00:23 <cr1901_modern> https://github.com/cr1901/yosys-experiments/blob/master/clk2fflogic/multiclk/multiclk.sby#L9

00:26 <awygle> mk great, thank you

00:27 <cr1901_modern> Anyways, clk2fflogic adds $ff cells and edge trigger logic. $ffs are flip-flops _implicitly_ clocked by $global_clock (so they have an 1 input and 1 output port, instead of 2 inputs, 1 output).

00:35 <awygle> well i guess i'll try and get the existing asyncfifo tested under formal with multiclock somehow....

00:36 <awygle> adding the option should be easy, not sure what changes need to be made to the fifo model (or a new one written)

00:39 <cr1901_modern> I don't remember how global_clock works in nmigen

00:45 <awygle> nor i

00:45 <awygle> but everything there is to know should be in the formal platform, presumably

05:23 <Ultrasauce> more onboarding docs would definitely be an appreciated addition

05:34 <awygle> What does that look like specifically?

05:34 <awygle> A tutorial? Conceptual docs? Best practices?

05:35 <awygle> (OK, all of the above, but what first lol)

09:11 <Degi> Is it possible to set termination resistors on the ecp5 for the differential pairs in nmigen?

09:26 <Degi> Found it, with Attrs(DIFFRESISTOR=100)

09:49 <Degi> Oh no, it says "no enum named PIOB.DIFFRESISTOR"

09:53 <daveshah> Sounds like you might be applying the constraint to the negative rather than positive side?

10:00 <Degi> Nvm, I forgot to add IO_TYPE="LVDS"

10:00 <Degi> Now I have a neat 110 ohms there, nice

13:17 <Degi> What does an "ir.py, line 396, in add_defs assert defs[sig] is self AssertionError" mean

13:38 <whitequark> a bug in nmigen

13:42 <Degi> And somehow now I get an assertion failure for is_string from nextpnr.h:362 (but the log looks fine)

14:14 <whitequark> you cn report that to nextpnr developers

14:14 <whitequark> it shoul at least result in a better error

14:20 <daveshah> It's been noted

17:28 <awygle> o/

17:37 <awygle> whitequark: so you've talked about documentation a fair bit but is there a structure you had in mind? should i just write e.g. "NEW_PLATFORM.md" and drop it in doc/ ?

18:07 <whitequark> awygle: no

18:07 <whitequark> sorry, can't discuss this right now

18:07 <awygle> mk, no rush

18:07 <whitequark> when will i be able? when i can afford food again

18:08 <awygle> oof. yes, obviously correct priorities.