ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at · logs at
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<whitequark> awygle: yeah
<awygle> *scrolls back up* oh OK then how do I make it do clk2fflogic?
<awygle> (I was playing with the FIFO formal proofs for async FIFOs when I asked that)
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<awygle> welcome back btw, hope you're doing well
<whitequark> not really well but doesn't matter
<whitequark> unfortunately I don't entirely understand clk2fflogic
<awygle> :/
<awygle> my best understanding is that it decouples the clock(s) from the SMT timestep
<whitequark> right; I mean I'm not sure how to actually use it
<whitequark> iirc cr1901_modern knows it
<awygle> i used it a bit when i was first learning about yosys formal
<awygle> although time seems to have moved on somehwat
<awygle> basically i just added it to my yosys script, and then used "assume" in a $global_clock process to make the clocks toggle
<awygle> oh right i remember now you're driving all the formal stuff through SBY (i played with different engines one time)
<awygle> so it'd be `multiclock on` i guess
<awygle> whitequark: i feel like i've been pushing a bunch of "new development" stuff on you lately. anything i can do to help in nmigen that won't make more work for you?
<awygle> thinking of writing docs for making a local platform for a custom board (as soon as i figure out how to do that)... maybe that's useful