ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen
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<Degi> Hm nmigen complains about a signal being driven from multiple fragments, but each subsignal is driven by a different fragment...
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<whitequark> Degi: each subsignal? can you post an MCVE?
<Degi> MCVE? It gave a warning about flattening the hierarchy but actually worked in the end.
<ZirconiumX> Minimal, Complete and Verifiable Example
<ZirconiumX> I'm gonna be honest, that's an odd architecture
<ZirconiumX> Perhaps "unidiomatic" is a better term
<ZirconiumX> So, I think nMigen is doing this at the Signal level
<ZirconiumX> At which point the error makes sense
<whitequark> what ZirconiumX said is correct
<whitequark> the cause of the warning is that nMigen turns every Signal into a module port when it emits hierarchical Verilog modules
<whitequark> there is no way to do that, in general, if the bits of that signal are driven from different moules in first place
<whitequark> hence the warning and the flattening
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<mwk> hmm, what'd be wrong with using inout in this case?
<mwk> I mean, it's messy and all, but wouldn't it work?
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<whitequark> I thought Yosys doesn't support internal inout when I was implementing tht
<whitequark> I'm not sure if it does
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<_whitenotifier-3> [nmigen-boards] sjolsen opened pull request #51: resources.display: Apply inversion setting to dp - https://git.io/Jvig9
<_whitenotifier-3> [nmigen-boards] whitequark commented on pull request #51: resources.display: Apply inversion setting to dp - https://git.io/Jvigp
<_whitenotifier-3> [nmigen-boards] whitequark closed pull request #51: resources.display: Apply inversion setting to dp - https://git.io/Jvig9
<_whitenotifier-3> [nmigen/nmigen-boards] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/Jvigh
<_whitenotifier-3> [nmigen/nmigen-boards] sjolsen c330044 - resources.display: Apply inversion setting to dp
<mwk> whitequark: it should work AFAICT
<mwk> I mean, I can't immediately think of anything that would break it
<mwk> I'd even say it's a reportable bug if you do find something
<whitequark> hrm
<whitequark> okay, I will take note of this for the future rewrite of that part of the code
<whitequark> #191 requires that rewrite
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<_whitenotifier-3> [nmigen] whitequark closed pull request #329: Implement solution to AsyncFIFO resets, as in #328 - https://git.io/JvVCG
<_whitenotifier-3> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±3] https://git.io/Jviao
<_whitenotifier-3> [nmigen/nmigen] awygle 4601dd0 - Correctly handle resets in AsyncFIFO.
<_whitenotifier-3> [nmigen] whitequark commented on pull request #329: Implement solution to AsyncFIFO resets, as in #328 - https://git.io/JviaK
<awygle> oh! surprising. expected more changes lol
<whitequark> I did approve it on the last round, besides some comment wording
<whitequark> I think the logic is pretty bulletproof there
<_whitenotifier-3> [nmigen] Success. 82.67% (+0.19%) compared to 12c7902 - https://codecov.io/gh/nmigen/nmigen/commit/4601dd0a69689fec3471e9a365bf87c00c507eef
<_whitenotifier-3> [nmigen] Success. 100% of diff hit (target 82.47%) - https://codecov.io/gh/nmigen/nmigen/commit/4601dd0a69689fec3471e9a365bf87c00c507eef
<_whitenotifier-3> [nmigen] Success. 82.53% (+0.06%) compared to 12c7902 - https://codecov.io/gh/nmigen/nmigen/commit/4601dd0a69689fec3471e9a365bf87c00c507eef
<_whitenotifier-3> [nmigen] Success. 100.00% of diff hit (target 82.47%) - https://codecov.io/gh/nmigen/nmigen/commit/4601dd0a69689fec3471e9a365bf87c00c507eef