17:20 <_whitenotifier-3> [nmigen-boards] whitequark closed pull request #53: zturn_lite: fix typo - https://git.io/JvXFg

17:20 <_whitenotifier-3> [nmigen/nmigen-boards] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/Jv156

17:20 <_whitenotifier-3> [nmigen/nmigen-boards] rroohhh 3cca5ff - zturn_lite: fix typo

17:20 <_whitenotifier-3> [nmigen-boards] whitequark commented on pull request #53: zturn_lite: fix typo - https://git.io/Jv15i

22:33 <pdp7> hello, I'm trying to do this Hello, World

22:33 <pdp7> http://blog.lambdaconcept.com/doku.php?id=nmigen:nmigen_hello_world

22:33 <pdp7> pdp7@x1:~/dev/fpga/nmigen$ python3 blinky.py simulate -c 20 -v blinky.vcd

22:34 <pdp7> produces:

22:34 <pdp7> TypeError: Object (slice (sig led) 0:1) is not an nMigen signal

22:34 <pdp7> pdp7@x1:~/dev/fpga/nmigen$ python3 blinky.py simulate -c 20 -v blinky.vcd

22:34 <pdp7> Traceback (most recent call last):

22:34 <pdp7> File "blinky.py", line 19, in <module>

22:34 <pdp7> main(top, ports=(top.led))

22:34 <pdp7> File "/home/pdp7/.local/lib/python3.7/site-packages/nmigen/cli.py", line 74, in main

22:34 <pdp7> main_runner(parser, parser.parse_args(), *args, **kwargs)

22:34 <pdp7> File "/home/pdp7/.local/lib/python3.7/site-packages/nmigen/cli.py", line 68, in main_runner

22:34 <pdp7> with sim.write_vcd(vcd_file=args.vcd_file, gtkw_file=args.gtkw_file, traces=ports):

22:34 <pdp7> File "/home/pdp7/.local/lib/python3.7/site-packages/nmigen/back/pysim.py", line 1117, in write_vcd

22:34 <pdp7> vcd_file=vcd_file, gtkw_file=gtkw_file, traces=traces)

22:34 <pdp7> File "/home/pdp7/.local/lib/python3.7/site-packages/nmigen/back/pysim.py", line 95, in __init__

22:34 <pdp7> if trace not in signal_names:

22:34 <pdp7> File "/usr/lib/python3.7/_collections_abc.py", line 666, in __contains__

22:34 <pdp7> self[key]

22:34 <pdp7> https://www.irccloud.com/pastebin/PW71MDtL/

22:35 <pdp7> sorry to not use pastebin

22:35 <awygle> i think it wants a list there instead of ()s

22:37 <awygle> yes

22:37 <awygle> replace () with [] on the ports, pdp7

22:37 <pdp7> the blinky program is:

22:38 <pdp7> https://www.irccloud.com/pastebin/I2eAl4Do/

22:38 <pdp7> awygle: ok thanks

22:38 <pdp7> nice!

23:23 <ktemkin> (it'll take any iterable for ports; and not just lists -- that's just missing the terminal ',' that makes python interpret it as a tuple rather than just a single element)

23:24 <ktemkin> so `ports=(top.led,)` is okay, since that generates a 1-element tuple; but `ports=(top.led)` is equivalent to `ports=top.led`, which is a signal where it expects an iterable of signals

23:27 <awygle> ah, thanks

23:46 <Vinalon> Hello! I have a quick question about using nMigen with iCE40 chips: does anyone know if it is possible to use their internal oscillators as a clock source?

23:47 <Vinalon> All of the board definition files that I can see in the 'nmigen_boards' package seem to use an external oscillator, and define the 'default_clk' value as a pin Resource.

23:47 <Vinalon> Thanks!

23:49 <Degi> Hm I think you can

23:49 <whitequark> it is possible; do you have a board that does not have any oscillator at all, or do you just want to use one of existing boards with SB_LFOSC/SB_HFOSC

23:49 <whitequark> ?

23:52 <Vinalon> I'm thinking of Gnarly Grey's 'Upduino' - it has a 12MHz oscillator which is broken out onto one of the board's pins, but it isn't connected to the FPGA by default

23:52 <Vinalon> It looks like their examples use the HFOSC oscillator, if I'm reading them right

23:52 <Vinalon> (And it uses an iCE40UP5K-SG48)

23:52 <whitequark> ok, so this will ideally require a small modification to the nMigen vendor code for iCE40

23:53 <whitequark> basically this patch: https://github.com/nmigen/nmigen/commit/b72c3fc7f697442ccc0c0fc583fc7b70002b841e but ported to iCE40

23:53 <whitequark> then you'll be able to say `default_clk = "SB_HFOSC"` in the board file

23:57 <Vinalon> Okay - so, it could just use 'Instance("SB_HFOSC")' in the same way?

23:59 <Degi> I think for now you'd need a Instance("OSCG", p_DIV=<value from 1-128>, o_OSC=<your clock signal>)