ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at · logs at
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<_whitenotifier-3> [nmigen-boards] whitequark closed pull request #53: zturn_lite: fix typo -
<_whitenotifier-3> [nmigen/nmigen-boards] whitequark pushed 1 commit to master [+0/-0/±1]
<_whitenotifier-3> [nmigen/nmigen-boards] rroohhh 3cca5ff - zturn_lite: fix typo
<_whitenotifier-3> [nmigen-boards] whitequark commented on pull request #53: zturn_lite: fix typo -
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<pdp7> hello, I'm trying to do this Hello, World
<pdp7> pdp7@x1:~/dev/fpga/nmigen$ python3 simulate -c 20 -v blinky.vcd
<pdp7> produces:
<pdp7> TypeError: Object (slice (sig led) 0:1) is not an nMigen signal
<pdp7> pdp7@x1:~/dev/fpga/nmigen$ python3 simulate -c 20 -v blinky.vcd
<pdp7> Traceback (most recent call last):
<pdp7> File "", line 19, in <module>
<pdp7> main(top, ports=(top.led))
<pdp7> File "/home/pdp7/.local/lib/python3.7/site-packages/nmigen/", line 74, in main
<pdp7> main_runner(parser, parser.parse_args(), *args, **kwargs)
<pdp7> File "/home/pdp7/.local/lib/python3.7/site-packages/nmigen/", line 68, in main_runner
<pdp7> with sim.write_vcd(vcd_file=args.vcd_file, gtkw_file=args.gtkw_file, traces=ports):
<pdp7> File "/home/pdp7/.local/lib/python3.7/site-packages/nmigen/back/", line 1117, in write_vcd
<pdp7> vcd_file=vcd_file, gtkw_file=gtkw_file, traces=traces)
<pdp7> File "/home/pdp7/.local/lib/python3.7/site-packages/nmigen/back/", line 95, in __init__
<pdp7> if trace not in signal_names:
<pdp7> File "/usr/lib/python3.7/", line 666, in __contains__
<pdp7> self[key]
<pdp7> sorry to not use pastebin
<awygle> i think it wants a list there instead of ()s
<awygle> yes
<awygle> replace () with [] on the ports, pdp7
<pdp7> the blinky program is:
<pdp7> awygle: ok thanks
<pdp7> nice!
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<ktemkin> (it'll take any iterable for ports; and not just lists -- that's just missing the terminal ',' that makes python interpret it as a tuple rather than just a single element)
<ktemkin> so `ports=(top.led,)` is okay, since that generates a 1-element tuple; but `ports=(top.led)` is equivalent to `ports=top.led`, which is a signal where it expects an iterable of signals
<awygle> ah, thanks
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<Vinalon> Hello! I have a quick question about using nMigen with iCE40 chips: does anyone know if it is possible to use their internal oscillators as a clock source?
<Vinalon> All of the board definition files that I can see in the 'nmigen_boards' package seem to use an external oscillator, and define the 'default_clk' value as a pin Resource.
<Vinalon> Thanks!
<Degi> Hm I think you can
<whitequark> it is possible; do you have a board that does not have any oscillator at all, or do you just want to use one of existing boards with SB_LFOSC/SB_HFOSC
<whitequark> ?
<Vinalon> I'm thinking of Gnarly Grey's 'Upduino' - it has a 12MHz oscillator which is broken out onto one of the board's pins, but it isn't connected to the FPGA by default
<Vinalon> It looks like their examples use the HFOSC oscillator, if I'm reading them right
<Vinalon> (And it uses an iCE40UP5K-SG48)
<whitequark> ok, so this will ideally require a small modification to the nMigen vendor code for iCE40
<whitequark> basically this patch: but ported to iCE40
<whitequark> then you'll be able to say `default_clk = "SB_HFOSC"` in the board file
<Vinalon> Okay - so, it could just use 'Instance("SB_HFOSC")' in the same way?
<Degi> I think for now you'd need a Instance("OSCG", p_DIV=<value from 1-128>, o_OSC=<your clock signal>)