ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at · logs at
<mithro> ktemkin: Hi!
<_whitenotifier-3> [nmigen] whitequark commented on issue #336: FSM state transition weirdness -
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<ktemkin> hi ^^
<whitequark> awygle: wait, I think the new mental model is also not entirely right
<whitequark> oh, sorry, I misread
<whitequark> should be right
<awygle> ok good
<awygle> lol
<awygle> is there value (in the abstract, not necessarily for nmigen-soc specifically) in the second thing, do you think?
<awygle> a generic "this is a thing with an address" concept?
<whitequark> I'm not entirely sure yet; I think this needs to be confirmed by trying to build it and seeing if it's usable
<awygle> sensible
<whitequark> there *is* something in nmigen-soc you can already use for that
<whitequark> the hierarchical memory maps
<awygle> oh is that what those are for? how do you attach them to a "real" bus?
<whitequark> jfng: re #10: I did not forget about that issue and as soon as things get less hectic I'll make sure to push it forward
<whitequark> awygle: you don't attach them exactly; they are metadata
<whitequark> in principle you can describe a topology even in e.g. external ASIC with those maps
<awygle> i see
<whitequark> but nmigen-soc primitives come with helpers that automatically build the right maps for you
<whitequark> which should reduce boilerplate and bugs esp in case when you have windows with strides and/or change in width
<awygle> well i'll just kinda play around til i get something i'm happy with
<awygle> and then maybe say "hey is this dumb"
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<_whitenotifier-3> [nmigen-boards] rroohhh opened pull request #53: zturn_lite: fix typo -
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