00:50 <mithro> ktemkin: Hi!

02:18 <_whitenotifier-3> [nmigen] whitequark commented on issue #336: FSM state transition weirdness - https://git.io/JvXaw

04:15 <ktemkin> hi ^^

05:31 <whitequark> awygle: wait, I think the new mental model is also not entirely right

05:31 <whitequark> oh, sorry, I misread

05:31 <whitequark> should be right

05:33 <awygle> ok good

05:33 <awygle> lol

05:34 <awygle> is there value (in the abstract, not necessarily for nmigen-soc specifically) in the second thing, do you think?

05:34 <awygle> a generic "this is a thing with an address" concept?

05:35 <whitequark> I'm not entirely sure yet; I think this needs to be confirmed by trying to build it and seeing if it's usable

05:35 <awygle> sensible

05:35 <whitequark> there *is* something in nmigen-soc you can already use for that

05:35 <whitequark> the hierarchical memory maps

05:35 <awygle> oh is that what those are for? how do you attach them to a "real" bus?

05:36 <whitequark> jfng: re #10: I did not forget about that issue and as soon as things get less hectic I'll make sure to push it forward

05:36 <whitequark> awygle: you don't attach them exactly; they are metadata

05:36 <whitequark> in principle you can describe a topology even in e.g. external ASIC with those maps

05:36 <awygle> i see

05:36 <whitequark> but nmigen-soc primitives come with helpers that automatically build the right maps for you

05:37 <whitequark> which should reduce boilerplate and bugs esp in case when you have windows with strides and/or change in width

05:38 <awygle> well i'll just kinda play around til i get something i'm happy with

05:38 <awygle> and then maybe say "hey is this dumb"

15:03 <_whitenotifier-3> [nmigen-boards] rroohhh opened pull request #53: zturn_lite: fix typo - https://git.io/JvXFg