<Lofty>
The whole thing that sparked project Mistral was the MiSTer project emulators
<trabucayre>
Hi
<Lofty>
And those are designed for the DE10-Nano
<Lofty>
Hello
<trabucayre>
I try to find some informations about sof file format and about JTAG instructions.
<Lofty>
SOF is basically RBF with some metadata
<jordigw>
Okay. It seems it's not the same model :-(
<Lofty>
No, but there are only 5 dies in the Cyclone V family, if I remember correctly
<Lofty>
So you might end up with a pretty serious upgrade
<jordigw>
three boards three different version :-/
<Lofty>
Again: not really
<Lofty>
I'm pretty sure when we properly RE this that the chips will all be the same: the sx150f die
<jordigw>
I will try.
<Lofty>
As for JTAG; that's presently unknown information, sorry
<trabucayre>
I have analyzed some part of the sof file but I'm unable to do the link between this file and svf
<trabucayre>
:(
<daveshah>
It's possible they split out the commands somehow before creating the svf?
<trabucayre>
maybe
<trabucayre>
I need, maybe, to dump jtag traffic with wireshark (as I done for gowin FPGA)...
<trabucayre>
(and anlogic)
<Lofty>
Oh, now I recognise the username
<Lofty>
You wrote openFPGALoader, right?
<trabucayre>
Lofty: true :)
<Lofty>
pepijndevos mentioned you I think
<trabucayre>
me I don't know but openFPGALoader yes :)
<Sarayan>
Lofty 7 dies, not 5
<Lofty>
...I swear it was 5, but okay
<Sarayan>
And I'm tackling all 7, so that I generalize correctly anyway
<Sarayan>
so as long as it's cyclone v, it's good
<Sarayan>
I may have to do cyclone10 at some point, but later :-)
<Sarayan>
after cv is done and buried
<trabucayre>
Sarayan: I'm interested by cyclone10 :)
<trabucayre>
cycloneV too in fact
<daveshah>
Do you know if there are differences in the internal data formats?
<daveshah>
or would the differences be more on the Yosys/nextpnr side (at least in the case of 10lp)?
<Sarayan>
I haven't looked at 10 at all
<Sarayan>
but it's used in the future analog pocket, hence my interest
<Sarayan>
Lofty: look at the 7 subdirectories in quartus/common/devinfo/cyclonev/cyclonev_*, these are the dies
<daveshah>
Oh, if anyone wants to play with big devices, it looks like Quartus Pro is available on Azure (similar to the Xilinx deal with AWS for Vivado)
<Lofty>
daveshah: 10 LP is quite different to 10 GX
<daveshah>
10 GX is closer to Cyclone V, right?
<Lofty>
Correct
<Lofty>
10 LP is more like Cyclone IV
<daveshah>
yeah
<daveshah>
I think Cyc IV and III are the same RTL with different standard cells, as their JTAG IDCODE are the same (I remember having the pick between the two in Quartus programmer when using Cyc III 5 years ago)
<trabucayre>
daveshah: true. Same idcode ...
<daveshah>
It would be odd to make substantial design changes but keep the IDCODE the same
<daveshah>
Unless someone just forgot to change it
<trabucayre>
I've this issue for openFPGALoader. Not possible to determine which fpga
<daveshah>
Quartus has a dialog box...
<Sarayan>
anyone knows of a cyclonev idcode table?
<Lofty>
Sarayan: knowing you, one will magically appear somehow :P
<daveshah>
Is there one in one of the datasheets? Xilinx and Lattice both have a "configuration user guide" type document with them