<wpwrak>
aw_: i have a little smt question: given an 0805-sized chip with 6 contatcs, like the one on the lower right of http://media.digikey.com/Renders/Wurth Electronics Renders/0805SMD.jpg
<wpwrak>
aw_: would you consider a gap - across the width - between pads of 0.8 mm to be okay ? the chip's width is 1.25 mm
<wpwrak>
aw_: when i soldered that component, it felt as if there wasn't much pad under the chip. but maybe that was just an illusion (and my etching technique may also have increased the gap a little)
<aw_>
wpwrak, 0.8 * 39.37mil = 31.496 mil which is okay in regular pcb industry. And probably be as an illusion while etching tech. by DIY.
<aw_>
wpwrak, a gap of pads you can always tell yourself to keep a general specification as nominal 5 mil which is current PCB maker can produce it.the
<aw_>
wpwrak, the 748421245 the minimum dimension is 0.2 mm (~ 7.84 mil)...I was only curious that how tuxbrain_away picked up a qualified pcb maker to make your design UBB.
<aw_>
when you trying to deal with a possibility of producing boards, building a part footprint with more than 5 mils is better. as this 748421245 is producible. :-)
<aw_>
not sure if my replies answers your question? ;-)
<wpwrak>
(5 mil) in this case, we have about 10 mil. so it should be safe then.
<wpwrak>
(pcb maker) the ubb result is encouraging. if they can make ubb, they can also make atben/atusb :)
<wpwrak>
(answers) yes, thanks a lot ! i just wanted to double-check that i'm not building a problem there
<aw_>
exactly. so what i would like to encourage such great results is that we keep to design at 5 or even 7mil gap (clearance, ring spec...etc) then the design will be any convenience and ease to produce anywhere not only Asia. ;-)
<wpwrak>
aw_: btw, have you had a look at the atben/atusb boards ? do they look okay ?
<aw_>
yeah..good.
<aw_>
wpwrak, sorry that haven't yet. ;-)
<wpwrak>
aw_: (5/7 mil) yeah. by testing things with my DIY process, i'm kinda limited to such sized anyway ;-)
<aw_>
wpwrak, i am trying to get m1 rc3 to be well-preparation done...after quite stuff done after sourcing can back look your masterpiece.
<wpwrak>
;-)
<aw_>
sure. you always can imagine the difference between how hard/feasibility it could be happened from diy'work to the general industry. it's all good.;-)
<aw_>
contrary to your work idea, i still haven't have this capability(RD.) to from diy work to industrial production. ;-)
<wpwrak>
it's nice for small and reasonably simple things. doesn't scale so well towards larger/complex things, though, due to the low yield
<wpwrak>
i.e., compact RF designs with lots of ground are messy
<wpwrak>
aw_: you say that the origin for positioning coordinates should be the center of a pad. why ? that's likely to be inaccurate anyway
<wpwrak>
aw_: (inaccurate) because the component's reference/anchor point is somewhere else and the pad center is not whole number of grid steps away from this point
<wpwrak>
aw_: unless you change the grid to something very small, etc., but that's looks like a high error risk
<aw_>
wpwrak, yes, you are right. but as a smt manufacture I don't need to be precisely correct. but if using a DIY draft driller you need precisely.
<aw_>
thanks that you mentioned this. let me edit it more info on this page. ;-)
<aw_>
smt vendor they can pick fine tune as very well even just offset a lot. :-)
<wpwrak>
aw_: hmm. i wonder, why try to hit the pad at all ? isn't it enough for the origin to be some well-defined point ? e.g., a corner of the board itself ?
<aw_>
wpwrak, umm..i remembered that I studied this for a while even I've never used a CNC driller....yes, I just watched that I already wrote notice in that page (at the bottom).
<wpwrak>
aw_: no, i mean for SMT, the AI file, not drilling/routing
<wpwrak>
aw_: (for cnc, i actually do a lot of post-processing/tweaking ;-)
<aw_>
you could imagine that smt machine which has powerful whole shifting offset with all parts' coordinates.
<wpwrak>
aw_: also, how did you specify the package sizes and reeling to the smt fab ? did you send them a copy of the data sheets ?
<aw_>
i also have your questions about first meeting smt machine.
<aw_>
i usually sent AI and gerber files then they can just fine tune all of them with bom. :-)
<wpwrak>
aw_: (offset) yes, i think that's inevitable. so there's no strict need for the origin to be on a pad ?
<aw_>
no datasheet at all.
<wpwrak>
aw_: (ai+gerber) heh, nice ;-)
<wpwrak>
aw_: (datasheet) so how do they get the dimensions ? do they look them up themselves ? also, do you specify the component height somewhere ?
<aw_>
exact on "no strict need for the origin to be on a pad", but please you should always let/move mouse cursor to the pad located at the most left and bottom side. Secondly, File->Fabrication Outputs->Modules Position, then the *.pos file is generated under main folder.
<aw_>
i don't need to specify any component height. their smt machine have a lot of database on huge footprint they already existed.
<aw_>
but there's one important step on calibration their each part while fine tune my part: how they do it. It's easy!
<wpwrak>
aw_: i was thinking of putting the origin just at the corner of the pcb. that's a point that's perfectly on the grid. if i pick a pad, it'll be somewhere odd. they need to correct in any case, but at least it'll be a clearly defined location.
<wpwrak>
aw_: (huge database) okay, let's hope for the best then :-)
<aw_>
they picked up a IPC standard footprint then let smt machine do a comparison with its database's footprint with picked part with optical capture then fine tune part's dimension. Surely this process is done by located our AI file to them.
<wpwrak>
(optical capture) ah, nice. let's see then how their machine likes my footprints :)
<aw_>
and their smt technician will do auto or self -auto tune the AI file in advance before feeding a 'translated AI(coordinates)' file into smt machine.
<aw_>
hey, your principles always be a good detail thing on "it's nice for small and reasonably simple things. doesn't scale so well towards larger/complex things, though, due to the low yield"
<wpwrak>
aw_: so they'll do some real work for all the money. nice :)
<wpwrak>
aw_: ah, what's the role of the "parts polarity" file ?
<aw_>
hehe....Smt industry moves dramatically for many years , yes . that's they relied on machine not original/principle concepts. :-)
<wolfspraul>
aw_: can we get those 'translated AI(coordinates)' file back from them?
<wpwrak>
aw_: (polarity) would that be for 0402/0603/etc. parts ? how did you generate it ?
<wolfspraul>
in general I would say - if the PCB or SMT supplier generate intermediate/corrected files, as part of our job, it would be great if they could zip them up and return to us
<aw_>
i was tried to get them...but I finally didn't get them.
<wolfspraul>
aw_: even if those files are in proprietary formats, say the format of a particular pick&place or AOI machine
<wolfspraul>
aw_: why not? what did they say?
<wolfspraul>
just keep asking every time :-)
<aw_>
but as i know that "translated (AI) file is not every types of smt machine is all the same. it depends on brand smt machine itsself.
<wolfspraul>
and escalate to the manager. no hesitation. if they like us a little less, I think we can still survive :-) (just keep them barely above kicking us out)
<aw_>
surely...i won't forget this(asking)
<wolfspraul>
yes I can imagine those files are proprietary
<wolfspraul>
but that's ok
<wolfspraul>
at least it's a start where they know they should return intermediate files generated as part of our jobs to us
<aw_>
Fuji/ Simens / etc..
<wpwrak>
wolfspraul: (what did they say) i can vividly imagine :-) "ha ha". then they politely forgot about it. eventually, adam also politely dropped the issue. the chinese way ;-)
<wolfspraul>
no I think there is actually no big secrecy. it's just unusual and creates workload for them.
<wolfspraul>
I am sure if they work for, say, our famous Apple, they have to make every last bit 24/7 accessible inside Apple's intranet
<wpwrak>
wolfspraul: hence the "forget about it" treatment :)
<aw_>
i could only ask them when I stay at smt vendor there. I don't want to waste time to discover this. some sort of proprietary.
<wolfspraul>
sounds good
<wolfspraul>
we slowly dig into this, it will increase the quality of the files we are sending to them in the long run
<wolfspraul>
and there are probably quite a few more standards/conventions to discover, if we only knew what they were...
<wpwrak>
someone needs to build a nice cheap DIY pick and place, then we could send them actually tested AI files ;-)
<wolfspraul>
also don't forget AOI
<wpwrak>
AOI ?
<wolfspraul>
automatic optical inspection
<wolfspraul>
they have quite impressive systems/software running there, and very important feedback loop for the pick & place machine
<wpwrak>
ah, yet another step
<wolfspraul>
without AOI, the pick&place operator would be relatively blind
<wpwrak>
so both are integrated into the same unit ?
<wolfspraul>
I think in practical reality the aoi is quite important, and part of an integrated process.
<wolfspraul>
not same unit, aoi is a different machine
<wolfspraul>
but the accuracy of p&p, and aoi feedback, go together in reality at the line
<wolfspraul>
aw_: do you agree?
<kristianpaul>
hmm, for thats is good the aptina stuff i hope :-)
<wolfspraul>
nah. those are very polished systems. from scratch it will take you 10+ years to develop something that is competitive with state of the art today.
<wpwrak>
so p&p has a local optical system for the individual tuning work and then aoi checks the big picture ?
<wolfspraul>
and by then the 'state of the art' aoi machines will have evolved a lot more
<kristianpaul>
now i wonder how those smt machines driven by a Z80, that you can actually still buy, survive..
<wpwrak>
(10+) i've heard that so many times ... :)
<kristianpaul>
:)
<wolfspraul>
yes but designing our own aoi machine is a sure way to get lost, imo
<aw_>
as i know, aoi machine is designed for mass productive purposes which is the process afterwards reflow process to verify if mis-mounted/un-balanced placements.
<kristianpaul>
oh, sure
<wolfspraul>
why not design our own xray machine, and many others. reflow oven, and so on.
<kristianpaul>
I just heard that once ;-)
<kristianpaul>
no no
<wolfspraul>
I don't know how many p&p machines have integrated optics to verify placement accuracy.
<wolfspraul>
maybe some high-end ones do. but keep in mind there is still the reflow oven after p&p.
<wpwrak>
wolfspraul: (oven) that's being done already
<wolfspraul>
that's a lot of movement, shaking, heat, etc.
<wpwrak>
wolfspraul: (xray) that sounds like the sort of thing you could get sebastien interested in :)
<wolfspraul>
so integrating optics into p&p only makes that much sense. you need a second optical check after the oven.
<kristianpaul>
he :-) (xray)
<wolfspraul>
aw_: if you think I mischaracterize something, let me know...
<wpwrak>
wolfspraul: (aoi) there's quite a bit of computer vision software out there. might be fun for people in the field, e.g., from academia
<wolfspraul>
of course. definitely doable, but in the grand scheme of things it's by far not at my top.
<aw_>
wolfspraul, so far there's no mischaracterize i read words. go on.
<wolfspraul>
there must be like 20+ other automated machines that create higher value when fully integrated into a free tools process than aoi.
<wpwrak>
wolfspraul: (p&p and optics) it would seem that you need some optical feedback already for proper pickup and for coordinate system translation. if you do it all via AOI after reflow, you have a heck of a feedback loop.
<wolfspraul>
yes maybe there are integrated optics in p&p
<wolfspraul>
but like I said - lots of vibration, shaking, movement and heat after that stil
<wolfspraul>
and the line is creating a fully soldered product, not something where the p&p machine says it's perfect, but the user cannot boot
<wolfspraul>
the movement of the conveyor belt, and application of heat in the reflow oven, may shift components just beyond acceptable tolerances
<wolfspraul>
so it all needs to have one big feedback loop, back from the 'aoi' (=after oven)
<wolfspraul>
the PCB is also not perfectly flat, which is what limits larger panels in many cases
<aw_>
as a EMS system which foxconn used , they used a tracking s/w system with a label(bar codes) to let every stations connected together and get feedback once afterwards process wrong.
<wolfspraul>
because depending on where on the curve a component sits, it may move differently in the oven. aoi will (should) catch it.
<aw_>
if that wrong is extremely like wrong color of part's surface then feedback to smt chine stoped. then operator check it.
<wpwrak>
wolfspraul: you probably need a fair bit of the same technology already for the pickup. well, there are also mechanical solutions. not sure how well they work, though
<kristianpaul>
rjeffries__: what happened with UBB run?
<wpwrak>
wolfspraul: (feedback) yes, you need the big loop too. what i mean is that the big loop would be a poor substitute for the local loop.
<kristianpaul>
you need buses
<wolfspraul>
you forget the action after the p&p machine
<wolfspraul>
there is a conveyor belt
<wolfspraul>
movement, shaking, vibrations
<kristianpaul>
lots of probes to read..
<wolfspraul>
the a lot of heat
<kristianpaul>
and heat to handle..
<wolfspraul>
there is no point to make the p&p machine perfect beyond a certain point
<rjeffries__>
my price was bad so I concede the global market to tuxbrain
<aw_>
wpwrak, exactly you discovered at all. nothing else i needed to provide to smt vendor. easy?!
<kristianpaul>
i guess is all based on current diferences (buses)
<rjeffries__>
he has cornered the UBB market
<kristianpaul>
wolfspraul: or may be hack an already p&r (just saying)
<wolfspraul>
we are just talking about understanding the file formats of commone p&p and aoi systems better
<wolfspraul>
I definitely believe in that. just getting the files, understanding them. so we are able to create higher quality (more easily usable) files ourselves, with free tools.
<wolfspraul>
I still don't know much about the file formats used in AOI machines, for example. seems the SMT places hold onto them...
<aw_>
wpwrak, i could only say that you could marked all polarity of parts needed you think, I only added polarities on parts like capacitor/diode..other ic pakages i even without adding more marks. but it's good that building the polarity while editing part library/module. ;-)
<wolfspraul>
of course from their view this is what ties you to a particular smt shop.
<wpwrak>
wolfspraul: again, my point is that the p&p machine would already benefit from some amount of vision, just not to make an excessive amount of errors locally
<wolfspraul>
sure I agree
<kristianpaul>
understand format, sure very important step :-)
<wolfspraul>
I'm past that
<wpwrak>
wolfspraul: i.e., when you pick up a component, it won't be perfectly centered and rotated
<wolfspraul>
my point was that there is a second interesting system regarding 'placement' after the oven, called 'aoi'
<wpwrak>
wolfspraul: if you catch that only after reflow, you have a problem
<wpwrak>
wolfspraul: thus i don't believe this is an open loop in p&p
<wolfspraul>
yes
<wolfspraul>
it's not
<wolfspraul>
aoi catches different things, and has its own place in the process
<wolfspraul>
but very sophisticated (lots of software), and very important. that was my only point.
<wolfspraul>
I don't think you can have a professional run of anything, say 1K or more, without AOI.
<wolfspraul>
aw_: what do you think?
<wolfspraul>
have you seen runs or lines without AOI step after the oven? say they skip it, after they feel pick & place is stable...
<wolfspraul>
or they always keep the aoi step running, as part of the normal production process?
<wpwrak>
wolfspraul: (aoi) yup, that's necessary as well. and it probably shares a fair amount of software (at least at the functional level) with the optics for the local loop in p&p. so if you make a p&p, you'd have to solve some of those problems already.
<wpwrak>
aw_: ah, you included the polarity in the footprint. in the silk screen ?
<wolfspraul>
wpwrak: no I don't think so. the aoi & p&p seem to be from different vendors, and definitely totally different software. at least from what I've seen so far (I keep learning...)
<aw_>
AOI machine is based on a base qty said over 200pcs mounted board or even 500 pcs to fine tune parameter/criteria to detetmine a qualified results from formal industry/or famous audit company.
<wolfspraul>
aw_: do you skip the AOI step in larger runs, or you always keep it running?
<aw_>
where I shew our rc1 of M1 run with AOI , it indeed doesn't make sense on fining tune anything at all. just for if checking mis-mounted.
<wolfspraul>
yes, but that's because they did a lousy job on the rc2 aoi :-) which is because it's not worth to setup a good aoi for a run of 40.
<wolfspraul>
(correct me if I'm wrong)
<aw_>
I always did AOI with the result report and replied to Motorola as audited report they defined from IPC doc.
<wolfspraul>
and one reason for that is because we don't know what types of files to supply to them to make a better aoi possible
<wpwrak>
wolfspraul: don't they have AOI also before the oven ? at least i think the fic fab had that. don't remember about the one in taiwan.
<aw_>
acutally I would like to cancel AOI run in lower than 500pcs.
<aw_>
wpwrak, AOI is afterwards smt reflow.
<aw_>
the lousy job is that we are not potential customers to them. yes, we just have 40pcs only. man!
<aw_>
even wejia I saw they were doing a celluar phone trial run with 800pcs!
<kristianpaul>
trial ;-)
<aw_>
it's "trial" run about samples to promote prototype phones.
<aw_>
800pcs only is "trial"..how we bit our business to let smt vendor to concentrate a 40pcs run?!
<aw_>
well..i know I always need to work with them.
<kristianpaul>
he, actually i still wonder how thy acept a run of 40pcs
<kristianpaul>
(hopefully i guess Qi is not the only one in the same path)
<kristianpaul>
of femtho runs :-)
<kristianpaul>
aw_: how long take the 800pcs to be finished? for smt
<aw_>
wpwrak, no , I dodn't include the polarity in the silkscreen. I don't need to add more polarities if you include them in silkscreen already. :-)
<wpwrak>
aw_: so how did you mark the polarity ?
<aw_>
kristianpaul, i didn't ask them how long..but it depends on machine. as i stayed before, 800pcs double sideds can be done in 5~6 hrs once fine tune is all done!
<aw_>
wpwrak, that case i added polarity in image file and sent to them.
<aw_>
wpwrak, so as your design, you could always add polarity into the same silkscreen layer.
<wpwrak>
aw_: ah, that's cheating ;-))
<aw_>
wpwrak, "cheating" works is always as "openning" process in "close" industry/field.
<aw_>
wpwrak, i didn't added/committed else in an original design. :-)
<aw_>
as a desiger if I do, I'll alway add polarity into silkscreen layer.
<wpwrak>
aw_: yeah, i'll do it in the silk screen. i don't like manual editing as part of the process. for me, the perfect workflow is just "make" :)
<aw_>
wpwrak, sure, be a s/w "make" style it is as you are. :-)
<wolfspraul>
aw_: yes agreed. if the aoi step is very sloppy, rather just leave it out.
<wolfspraul>
up to them. our next run is 80, so I hope we find good decisions to produce the highest number of sellable boards, in the most economical way.
<aw_>
wolfspraul, indeed it is. I'll decide surely then.
<wpwrak>
kristianpaul, tuxbrain_away: regarding the fab (pcb) files, they're not the final versions yet. they're sufficient for getting a quote, but you should update after that
<qi-bot>
[commit] Werner Almesberger: mlztx/mlztx: new utility to copy text in KiCAD board files to multiple layers http://qi-hw.com/p/eda-tools/f8f8a75
<wpwrak>
tuxbrain_away: (it's also included in the tarball/zip)
<wpwrak>
tuxbrain_away: note that they're a little different. for atben, i recommend an ENIG finish, while atusb probably doesn't need that
<wpwrak>
tuxbrain_away: but that should be specified by the SMT fab. they'll have some set of preferred finishes.
<wpwrak>
aw: is simple tin coating still okay for 0402 and 0.5 mm QFN or do they already require something better ?
<aw>
wpwrak, is this to your rf product on Surface Treatment? if yes, please use Immersion Gold rather than Immersion Tin. if you ask me why? I have no quite answers on this.
<aw>
cause I've always seen Immersion gold on rf pcb, never seen tim pcb before. ;-) It must be haven reasons behind.
<aw>
wpwrak, if even no rf-related at all, i still used immersion gold on m1 board.
<aw>
wpwrak, don't know if answered your question?
<wpwrak>
aw: (never seen tin) hehe ;-) yeah, i read lots of good things about ENIG
<wpwrak>
aw: if it wasn't RF, would you consider tin appropriate for components this size ?
<wpwrak>
tuxbrain_away: seems that we should upgrade the recommendation for ENIG to a strong recommendation :)
<aw>
wpwrak, for components? or pcb coating? sorry, can't follow up.
<aw>
what's ENIG? is it a name of journal?
<wpwrak>
aw: let me put the question in another way: what is the smallest component size where you would not use tin because it may cause reflow problems
<aw>
wpwrak, aha...i remembered when i stayed at close company, the QA department they had have rules on this details.
<aw>
so yes, you got serious question on points, but I still have used tim coated component with 0603 produced at least 2k in half years without reflow problems.
<wpwrak>
aw: ah, sorry, i didn't clarify that point: i mean the tin (or ENIG) as pcb finish
<aw>
so in a reality in practice, i quite won't focus on this. but as a researcher or professional designer, yes. if you already knew some info from others, just follow it.
<aw>
then I think it still won't be the problem at all since smt/re-flow machine tech them moved forwarding than ours.
<aw>
what carrier frequency of that ADP-SMAF-SMAF-ND you used?
<wpwrak>
ask N experts, get >= N opinions ;-)
<wpwrak>
(carrier) they don't specify. but sma usually goes up pretty high
<aw>
oah...yeah..tomb stoning..those experts even include Reliability / FMA Engineer!
<aw>
as a FMA is more concentrating on product life discussion.
<tuxbrain_away>
ok today I will as for quoting on PCB, 100 and 500 of each. once you are ready with smt info please let me know
<aw>
wpwrak, yes..came from even IPC expert. :-)
<wpwrak>
tuxbrain_away: you can ask the pcb fab about the exact specification of their tin. seems that there are several types of tin finishes, e.g., there's also a tin-on-nickel, that's apparently not as bad a HASL
<aw>
wpwrak, if even you pick OSP, that you should always let them to do the impedence report, otherwise i doubt they will ensure the trace you want.
<wpwrak>
(tuxbrain) i'd try to let the fabs fight it out among themselves. if that's not possible, i'd try enig. if that's a problem, i'd hope for the best with "tin"
<wpwrak>
i don't know how those impedance reports work
<wpwrak>
i'm a bit worried about the storage properties of OSP. doesn't it degrade quickly ?
<wpwrak>
in any case, i don't think we need to try to optimize for the last percent. the whole design isn't that precise anyway.
<wpwrak>
if someone with proper RF equipment has a go at tuning and optimizing things, that would change. but for now, i'm already happy if random variations stay below 5 dB
<aw>
once OSP sealed package is opened, you will lose them. yes.
<wpwrak>
that makes OSP a no-go
<aw>
hm.. < 5dB is quite a good variation.
<kyak>
xiangfu_: ping
<wpwrak>
we'll see what happens :) i'm sure there will also be quite some difference between my prototypes and proper pcbs. hopefully for the better :)
<aw>
wpwrak, true. from hard data, the differences will be discovered from reading amplitudes of SA. :)
<xiangfu_>
kyak: Hi
<xiangfu_>
I update the build host compile script file. now ti's compile again.
<xiangfu_>
2. remove all commit that relate with 'data/*'
<xiangfu_>
3. clean up the kernel patches. (like 2.6.37 problem)
<xiangfu_>
4. cleanup the u-boot patches. (for now I only make it work with nanonote. I think it's broken in n516/n526 "
<xiangfu_>
5. send ks7010 patch to upstream
<xiangfu_>
6. send target/linux/xburst/base-files's patches to upstream
<xiangfu_>
7. while(1) {compile;debug;}Â Â :)
<kyak>
yeah, it all sounds right
<xiangfu_>
8. what do you think we rename the 'data' to 'data-backfire' under 'nanonote-files'
<xiangfu_>
9. create a total new 'data' folder. (mean the config* and etc/* stuff)
<xiangfu_>
s/mean/i mean
<kyak>
do you plan to support backfire?
<xiangfu_>
at least keep is compile.
<xiangfu_>
I don't know what is the plan on backfire in OpenWrt side when the new release come out
<kyak>
maybe it is better not to create the separate data-backfire? If someone wants to build for backfire, he would checkout the according branch of openwrt-packages
<kyak>
there is also "release_2010-11-17" branch and others
<xiangfu_>
there is no "tracking_backfire" in my local. and we delete it for a very long time.
<kyak>
so it's for some reason left in web interface
<kyak>
you can see it the list of branches
<xiangfu_>
hmm... not sure. or maybe someone run 'git push -a'
<xiangfu_>
I will delete it.
<kyak>
why do we need the "tracking-trunk" anyway? is it temporary, before it becomes the "master"?
<xiangfu_>
'release_2010-11-17' is create by Mirko. for release 2010-11-17
<xiangfu_>
1. we have to have a 'tracking-trunk'
<xiangfu_>
2. then if the Openwrt new Release come out. move the 'master' to 'backfire'
<xiangfu_>
3. move the 'tracking-trunk' to 'master'
<tuxbrain_away>
wpwrak aw : I will go for ening then, as wpwrak said ... let's cross our finguers also I will ask to the smt provider for thier opinion but for that I need the smt files to make the question with the quote inquiry...
<kyak>
xiangfu_: ok, it's pretty clear
<kyak>
xiangfu_: why can't we just drop backfire here and now? :)
<kyak>
update "master" to "trunk"
<kyak>
by the time openwrt is ready for release, we will be ready, too
<kyak>
it seems that fixinf backfire is a waste of time
<kyak>
*fixing
<xiangfu_>
kyak: it will create a lot of merger . very very hard to cleanup. we can just merge the 'master' branch to 'trunk'.  the git commit history will go crazy. almost un-able to 'rebase' on 'trunk' again.
<kyak>
i doubt that it makes sense to release another backfire-based image
<kyak>
therefore, all activity in backfire is not needed
<kyak>
xiangfu_: yeah, i udnerstand. What i mean is to take the trunk and rebase our commits for backfire on top
<xiangfu_>
kyak:oh.
<kyak>
and start with that
<xiangfu_>
kyak: you mean switch to 'trunk' and work on 'trunk' now?
<kyak>
yep
<kyak>
don't do anything for backfire anymore
<xiangfu_>
hmm...
<kyak>
when openwrt makes the release, we will stay on release.. Won't follow the trunk any more
<xiangfu_>
yes. that is the plan. the only problem for me is can we create a release on trunk in 4~6 weeks.
<kyak>
well, even if we can't, we will have a head start of 4-6 weeks
<kyak>
if you mean that the openwrt will release in 4-6 weeks
<xiangfu_>
no. I mean our regular release interval is 4 ~ 6 weeks. so if we switch now. I just worry about can we finish all merge jobs in 4 ~ 6 weeks.
<kyak>
ah, ok. SO if you do plan to release another image based on backfire, that's another situation
<xiangfu_>
in fact I am not sure if we need another images based on backfire.
<xiangfu_>
maybe we should start switch now.
<xiangfu_>
ok. I think I will push a branch name 'trunk' and start build the 'trunk' branch in buildhost now.
<xiangfu_>
for now still keep the 'master' tracking backfire.
<wolfspraul>
xiangfu_: make the decision based on what is the easier path to the next stable release, as of today
<wolfspraul>
if the easier path is with backfire, stick with backfire. if the easier path is with upstream trunk, switch to trunk.
<kyak>
xiangfu_: will it be the trunk as it is, or the trunk with our commits for backfire on top?
<wolfspraul>
I don't see why we need to switch to a not even released yet upstream version fast, but I don't know the details so there may well be reasons.
<xiangfu_>
wolfspraul: yes. we have to test . that why I push the 'trunk' start work on that.
<xiangfu_>
kyak: 'trunk' as it is and start our plan 1~9. (we just talk about)
<wolfspraul>
actually I think kyak, dvdk may know well, or openwrt upstream folks.
<xiangfu_>
yes.
<wolfspraul>
I think we should value stability very high.
<kyak>
xiangfu_: sounds good
<wolfspraul>
but who knows, stability may show up in unexpected places ;-)
<kyak>
wolfspraul: a stable image can be built right away with backfire, only a few pactches requried :) But switching to trunk is really good for testing
<kyak>
dinner time..
<wolfspraul>
then I don't know why we need to rush the switch, and I propose to build the next image based on backfire as well
<wolfspraul>
it's not that we have too little work, as copyleft hardware
<wpwrak>
tuxbrain: the will need more data for a quote (like the BOM), but for questions about the proper finish, this should be more than enough information
<wpwrak>
tuxbrain: do you already know where you want to to SMT ? or will you ask the PCB fab for advice ?
<wpwrak>
roh: hooray, it's monday morning ! is tech support for mail.openmoko.org awake yet ?
<tuxbrain>
wpwrak: (smt) I have already contacted them time ago when I want to make an ir arduino shield that doesn't see the sun light, and yes was recomended by the pcb vendor
<tuxbrain>
I'm finishing a pair of prior task and and I will make the mail for asking/quoting.
<tuxbrain>
is be the bom you pass valid?
<wpwrak>
tuxbrain: the BOM is valid but it is a "shoppinug list" bom. some quantities are rounded up. also, the BOM is for 100 units.
<wpwrak>
tuxbrain: again, it should give them an idea of what's there
<wpwrak>
tuxbrain: it you only ask them general things like the recommended finish and such, they should be fine with incomplete data. just tell them that we're not quite done yet and that this is for illustration only.
<tuxbrain>
ok I will advice them about that, the will maybe have other providers than this also , and they have to quote me for 100 and 500,
<tuxbrain>
ok I will give to the mail a  "draft touch" :)
<tuxbrain>
but I bet we will end with 500 pcb and 100 smt
<wpwrak>
tuxbrain: that's my guess as well ;-)
<wpwrak>
tuxbrain: how do they wrap the pcb panels ? all in one bag or are they individually sealed ?
<tuxbrain>
all in one bag, why?
<wpwrak>
tuxbrain: makes me wonder how easy it is to remove only part of them. if the rest is exposed, it may get dirty and cause trouble if you want to smt them later.
<wpwrak>
tuxbrain: enig is chemically very stable, but dust and such may still affect it. i hope you don't have any smokers nearby ;-)
<LunohoD>
larsc: there is no CONFIG_JZRISC anymore
<tuxbrain>
mmm ok, if 500/100 is the final deal, I will as them in packages of 100 (or nearest number depending on how may in panel)
<wpwrak>
tuxbrain: (chemically stable) for comparison, the nowadays quite popular OSP (organic solderability preservative) will decay on its own if exposed to the atmosphere
<wpwrak>
tuxbrain: (bags) maybe ask them if they could just wrap them individually. shouldn't be a major cost factor
<wolfspraul>
wpwrak: I think most pcbs have another layer on top to make it storable
<wolfspraul>
Adam knows more details
<wpwrak>
tuxbrain: then you could also supply kristianpaul and maybe send some my way, so that i can make a set of references and see how the rf behaves
<wolfspraul>
you are only talking about the functional surface finish
<tuxbrain>
wpwrak: yes of course :) but first the had to be done
<wolfspraul>
but there is another surface finish to ease production handling, in particular storage before smt
<wolfspraul>
it is quite common to produce a large number of pcbs, and then use them up in several runs over some time
<wpwrak>
wolfspraul: hmm, possible. i think a batch we once got at openmoko and we never used didn't have that, though
<wolfspraul>
that may be, maybe because it wasn't ordered :-)
<wolfspraul>
I'm just saying there is another standardized layer on top, for exactly the kind of problem tuxbrain is looking at (500/100)
<wpwrak>
wolfspraul: (never used) when dash made some pcbs for us, because they didn't like the lead time the chinese fab gave us before bullying :)
<wpwrak>
wolfspraul: okay. that would be useful if it's available
<wolfspraul>
Adam may know more about it, or just google
<wolfspraul>
again: it is quite common to store pcbs for a while before smt
<wpwrak>
wolfspraul: naw, let tuxbrain ask the fab ;-)
<wolfspraul>
and there are surface layers for that
<wolfspraul>
it's not about sealed plastic bag or not, it's something on top of the surface (at least I have never heard about sealed packages for pcbs)
<wpwrak>
wolfspraul: layers that you would remove before fabbing or layers that don't need removing ?
<wolfspraul>
don't know, maybe both exist
<wolfspraul>
the pcbs take some bath first, no?
<tuxbrain>
yeah , let the experience tuxbrain manufacturer to deal with all that :P
<tuxbrain>
sob
<wolfspraul>
at smt, the very first thing is that they clean the pcb, I think
<wolfspraul>
in some bath?
<wpwrak>
tuxbrain: you're paying them good euros not cheap rmb, so you should get something in return ;-)
<wolfspraul>
maybe that's where this layer comes off
<wolfspraul>
I am guessing.
<wolfspraul>
but my point is: tuxbrain is not the first to encounter the problem of storing pcbs.
<larsc>
LunohoD: that patch was never strictly needed, but that it depends on CONFIG_JZRISC instead of CONFIG_MACH_JZ4740 is a mistake. In theory that patch could have some performance improvements
<LunohoD>
larsc: ok, thanks
<wpwrak>
wolfspraul: yeah. and i've seen boards get some rough handling, too. never seen an extra layer, though. i think with all the boards we had at openmoko, i should have crossed some.
<wolfspraul>
you can't see it much, it just looks like a little foggy layer
<wpwrak>
wolfspraul: (and i've also seen soldering on bare boards from the discard pile. so they certainly haven't seen any special washing)
<wolfspraul>
a little blurred, like a very thin film of glue
<wpwrak>
wolfspraul: alright. let's hope tuxbrain's fab has that foggy stuff, too
<wolfspraul>
and there may be multiple ways to improve storability
<wolfspraul>
this is all before the first application of heat
<wolfspraul>
a normal PCB is designed to be heaten up only once anyway, at least that's what the process is optimized for
<wolfspraul>
so once you are in 'resolder boards from discard pile' land, all bets are off anyway
<wolfspraul>
that's not what the process is optimized for, so naturally you may run into all sorts of problems :-)
<wpwrak>
wolfspraul: (discard pile) no, that was pcbs that never went to smt.
<wolfspraul>
alright then. let's see what tuxbrain learns.
<wolfspraul>
I'll ask adam tomorrow too.
<wpwrak>
wolfspraul: (soldering cycles) particularly true for OSP
<kyak>
damn! switching between branches touches all files and have to recompile :)
<kristianpaul>
morning
<kyak>
xiangfu: already running a build in trunk :)
<xiangfu>
kyak: great. without any patch ?
<kyak>
xiangfu: some things fail (fbterm so far, cause uClibc is not built with locale support by default). Should i add patches to trunk?
<xiangfu>
kyak: you local first.
<xiangfu>
kyak: after I remove the 'data/*' commits I think.
<kyak>
so you plan to put our commits for backfire (without data/) in trunk anyway?
<kyak>
before submitting them upstream
<xiangfu>
kyak: I needs cleanup those patches. the generate them by "git format-patch". then I can try to send them to upstream.
<xiangfu>
yes. needs cleanup first.
<kyak>
ok, so you will clean it up locally?
<kyak>
clean up - like moving config changes from uClibc-0.9.30.1 to config of uClibc-0.9.32
<xiangfu>
kyak: yes.
<kyak>
all right :)
<xiangfu>
kyak: but it needs some time. next week maybe or even later. I can not finish them in this week
<kyak>
no problem
<kyak>
maybe i can help, send you my local patches that i would have by the next week
<wpwrak>
tuxbrain: oh, and in case you haven't sent things to the pcb fab yet, maybe wait an hour. i'm changing the coordinate origins
<tuxbrain>
i think until this night I will be unable to send the mail :(, other task are taking me more time than expected (as always)
<wpwrak>
ah, interesting. never happens to me ;-)
<wpwrak>
interesting .. kicad generates rather wrongish coordinates in DXF. i wonder how the pcb fab solved that for ubb. maybe they didn't use the DXF after all (the gerbers are nicely in sync)
<qi-bot>
[commit] Werner Almesberger: kicad-patches: command-line selection of aux origin; support aux in DXF, too http://qi-hw.com/p/eda-tools/984a6de
<wpwrak>
for wolfgang_early_to_bed's consideration
<qi-bot>
[commit] Werner Almesberger: mlztx/cptx: new utility for KiCAD board files to copy content across text fields http://qi-hw.com/p/eda-tools/e6f05a0
<tuxbrain>
roh any advance in the atben/atusb encapsulation?
<kristianpaul>
wpwrak: in my side i never was asked for dxf files
<tuxbrain>
I'm still thinking that silicon cover better than a box... any argument against this apart of the less open/hackable feel?
<rjeffries>
wpwrak it seems your openmoko email is fubar
<rjeffries>
tuxbrain at teh beginning silicon cover is function although a little on the funky looking side
<tuxbrain>
rjeffries: sorry but my english skills doesn't able to really understand that sentence...
<tuxbrain>
rjeffries: btw you finally have the ubbs from germany isn't it?
<wpwrak>
kristianpaul: (dxf) they asked tuxbrain for it
<wpwrak>
tuxbrain: real men like silicone ;-)
<wpwrak>
rjeffries: (mail) i know, i know ... so you got a "hard" bounce already ? or just a warning ?
<tuxbrain>
wpwrak: the firmware flashing part is also pending to solve
<wpwrak>
tuxbrain: (firmware) i know, i know ... that's why i shipped all the samples with atusb-pgm cables
<wpwrak>
tuxbrain: a production testing process is also pending
<kristianpaul>
still waiting quoute
<kristianpaul>
tuxbrain: less open/hackable feel, yes
<kristianpaul>
(real men like doing his own case)
<kristianpaul>
wood/plastic :-)
<kristianpaul>
or a silicone mold
<wpwrak>
kristianpaul: silicone is quite hackable. you just cut it and peel it off. it comes off cleanly. then you can solder. afterwards, re-seal with new silicone.
<wpwrak>
kristianpaul: you can also cut open smaller areas, if you want to
<kristianpaul>
well several layers of silicon should make a good work..
<roh>
tuxbrain: huh? no. how?
<kristianpaul>
no multiply tat by...
<roh>
tuxbrain: i havent even recieved the boards
<kristianpaul>
s/no/now
<tuxbrain>
I'm afraid silico, is too easy removable or don't stand with day by day friction
<tuxbrain>
ok roh, I have thinked you have received them...
<tuxbrain>
wpwrak: already send to him?
<wpwrak>
tuxbrain: sure. left the country last wednesday, after the xxxl weekend
<tuxbrain>
wpwrak: firmware+production testing... if this has to be also quoted , isn't it?
<wpwrak>
tuxbrain: (fw+testing) no, that's what you do ;-)
<wpwrak>
kristianpaul: several layers may be less effective than just one
<tuxbrain>
wpwrak: ha! I know I know there has to be some trap in the deal in any place !!! arrrgh
<wpwrak>
tuxbrain: for atben, silicone should be more than sufficient. if you treat the board too roughly, something else will break
<wpwrak>
tuxbrain: atusb, dunno. depends on your insertion/removal force. in general, also there, gentle treatment is encouraged
<wpwrak>
tuxbrain: well, the fw flashing is easy. the testing yet TBD
<tuxbrain>
starts to search for older machines and space to flash/test hundreds of atbens/usb
<roh>
hm. tracking doesnt say anything useful
<wpwrak>
roh: maybe it's not even in the country yet. some of the postal routes are very circuitous.
<rjeffries>
tuxbrain I think today David K is going to the post office to mail me qty 1 UBB
<rjeffries>
I intend to pay him using Bitcoin just for the practice and per his preference
<tuxbrain>
thinks to recover the OM buzz fix party spirit and think on mount a NN WPAN flash/test party :P
<roh>
Bitcoin is russian mafia financed.
<roh>
but i will not write that on the ml
<rjeffries>
roh ho wcool is that?
<roh>
rjeffries: not. basically use is illegal in most countries and you will be fucked as soon as you need to do taxes.
<rjeffries>
it turns out that ?mining? bitcoin takes a very VERY long time, so I will go to an exchange, buy bitcoin
<tuxbrain>
is afraid there is no such NN critical mass to make such a party argh
<kristianpaul>
wpwrak: may with a non-transparent silicone all can change
<wpwrak>
flashing isn't too bad. press atben-pgm on the board, run avrdude, wait some 20 seconds, done
<wpwrak>
kristianpaul: you mean it would be better or worse ? i think a transparent one may be nice
<tuxbrain>
20 secs*100=2000sec=33'3333 hours
<wpwrak>
sounds survivable, doesn't it ? ;-)
<tuxbrain>
put 500 instead of 100 and it doen't sounds so good :(
<wpwrak>
testing may be a bit more involved, though. but should be automatable. do you have access to a spectrum analyzer or an usrp2 ?
<tuxbrain>
start thinks on a flashing machine.....
<wpwrak>
500 would be 1-2 days. not too horrible either. and think of the margin ;-)
<wpwrak>
tuxbrain: since you're maufacturer and distributor, you get to pocket the parts of both. with 500 units, we'd start to be talking about real money :)
<wpwrak>
tuxbrain: so you could start putting some meat to the potatoes ;-)