10:49 <strawberyargon> !hot

11:01 <kyak> !now

11:01 <kyak> i mean, !not

13:13 <promach> For UART, how to notify RX that TX has buffer underrun which means the received data is not valid until TX solves buffer underrun issue ?

13:15 <wpwrak> promach: in a uart, rx and tx are largely independent. one can be idle while the other is working, and if both are busy at the same time, they may be at different bits.

13:16 <wpwrak> promach: what they typically share is the clock divider for the bit rate and some control registers. but that's all.

13:17 <promach> I do not think they share control registers

13:17 <promach> wpwrak: let's sa it is between two platforms

13:17 <promach> say*

13:18 <wpwrak> i mean on the same device

13:18 <promach> ok

13:18 <promach> one more thing

13:18 <promach> For http://www.ti.com/lit/ds/symlink/pc16550d.pdf#page=17 , how is the output of baud_generator (16x baud) used in transmitter logic ? I only see there is a transmitter timing control block in the functional block diagram, but I am not sure how it works exactly. Anyone ?

13:19 <wpwrak> i see you means tx and rx on both ends. there, you don't need to tell rx anything about tx underruns, since each byte has a start bit that synchronizes the receiver

13:20 <promach> what is the purpose of generating 16x baud ?

13:21 <promach> I thought 16x baud is used to oversample RX data ?

13:22 <promach> wpwrak

19:13 <DocScrutinizer05> promach: the UART hardware for example does sampling in middle of the bit timing window, and for TX it uses the 16x clock for internal stuff like FIFO register2register transfers etc

19:14 <DocScrutinizer05> on T1 the sending register enabled data output, on T2 the receiving register samples&holds data from the bus. Stuff like that

19:16 <DocScrutinizer05> sending and receiving registers are local and internal here, like two registers of a FIFO

19:18 <DocScrutinizer05> T0: R(N)-out; T1: R(N-1)-strobe;

19:27 <DocScrutinizer05> http://www.ti.com/lit/ds/symlink/pc16550d.pdf#10 >> tIRS Delay from Initial INTR Reset to Transmit Start: 8 to 24 BAUDOUT Cycles<<

19:29 <DocScrutinizer05> also see "Figure 3. BAUDOUT Timing"

19:30 <DocScrutinizer05> ff