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<promach>
DocScrutinizer05: I need to find out why the book needs to use Figure b
<promach>
For UART, if Tx device transmits at 9600Hz, Rx device need to sample at sampling frequency of at least twice that of 9600Hz ?
<DocScrutinizer05>
yes
<DocScrutinizer05>
more like 16*
<DocScrutinizer05>
the circuit in the book lacks a DC-blocker cap and 3* R for biasing input. They simplified and messed it up due to too much simplification
<DocScrutinizer05>
2*R at least
<promach>
huh ? 2*R ? where ?
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<promach>
for UART Rx, what's the benefit of sampling more often?
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<DocScrutinizer05>
detecting edges, so you know more precisely where's *middle* of a bit time window
<DocScrutinizer05>
UART waits for leading edge of startbit, then samples all data bits at middle of the bit period. since the clock for the hw isn't async, it needs an as finfrained as possible oversampling to detect *leading* edge of startbit to map it to internal clock
<DocScrutinizer05>
2*R at input to bias
<DocScrutinizer05>
alas that would also attenuate the input signal, or at least change input impedance, so they ommitted it
<DocScrutinizer05>
for an analog amp you want all transistors (except in complementary bridges, and even there depending on whether it's more of a class A or AB or class B) to draw some quiescent current
<DocScrutinizer05>
tying input gate to GND doesn't make sense in that circuit in your book
<DocScrutinizer05>
the amp is in extreme clipping situation
<DocScrutinizer05>
re UART I wasn't as clear as I should. The clock needs to be 8 or 16 times higher than bitrate. So the leading edge of startbit can get determined to a 1/8 or 1/16 of bit-time precision. Then (for 16 times oversampling) the hardware samples all subsequent data bits at $time_of_startbit_edge + N(bit)*16 + 8
<DocScrutinizer05>
the "jitter" you have is bitrate/16 then, since the clock won't phaseshift on detecting startbit leading edge
<DocScrutinizer05>
*if* you had a clock oscillator you could stop, and then start it on detecting leading edge of startbit, then a oscillator clock frequency of bitrate*2 would suffice
<DocScrutinizer05>
then you,d sample first bit on clock period#3, 2nd bit on #5, 3rd on #7 a s o
<DocScrutinizer05>
since you use an exernal clock, you want oversampling to approximate that ideal behavior
<DocScrutinizer05>
it's all about the precision of your detecting the startbit leading edge
<DocScrutinizer05>
not exactly to the point, but related
<promach>
DocScrutinizer05: Why (for 16 times oversampling) the hardware samples all subsequent data bits at $time_of_startbit_edge + N(bit)*16 + 8
<DocScrutinizer05>
your (external) clock and the serial data bitrate 'clock' interfere aka "alias" with each other, since the external clock isn't synced to the bitrate. so with a clock frequency of bitrate * 2 your databit sampling could happen *anywhere' within the bit period, from leading edge to trailing edge. With 4 times oversampling it will happen anywhere from 25% to 75% of bit period, so a lot closer to the center already
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<promach>
Why With 4 times oversampling it will happen anywhere from 25% to 75% of bit period ?
<DocScrutinizer05>
first sampling point detects startbit level. now you add 1 bitperiods and sample again. When will this sample happen? Answer: anywhere between startbit-leading-edge+0 + 1_bit_period, and startbit+startbitduration + 1_bit_period
<DocScrutinizer05>
Why With 4 times oversampling it will happen anywhere from 25% to 75% of bit period ? ::: because then the startbit leading edge gets detected with a precision of bitperiod/4
<DocScrutinizer05>
you don't know when the startbit leading edge happens since the UART only **samples** to detect the edge
<DocScrutinizer05>
you only know with a precision of the sample period
<promach>
how do you get 75% for 4 times oversampling ?
<DocScrutinizer05>
0% to 25%, 25% to 50%, 50% to 75%, and 75% to 100%. So your precision is +/- 25%, aka from 25% to 75%
<promach>
I do not understand ?
<promach>
what about startbit+startbitduration + 1_bit_period ?
<DocScrutinizer05>
and you got an 'error margin' of 25% to both leading and trailing edge
<DocScrutinizer05>
sorry, I give up, I'm not up to the task of explaining this
<promach>
never mind. I found that to obtain Rout, Vin has to be shorted to ground
<promach>
which is Figure b
<DocScrutinizer05>
that's gibberish
<DocScrutinizer05>
I don't know who came up with this
<DocScrutinizer05>
it's faintly correct for *real* working circuits, but figure b is no working circuit, it's defect by design since it has no bias
<DocScrutinizer05>
and no DC decoupling to protect the bias
<promach>
Figure b is a test circuit to measure Rout
<DocScrutinizer05>
sorry, I got other stuff to do
<DocScrutinizer05>
you can't measure the Rout of a broken circuit
<DocScrutinizer05>
it's meaningless
<DocScrutinizer05>
the circuit is meant for an input voltage swing of maybe GND+0.7V to VDD-<whatever>. Outside of that voltage range the circuit doesn't work, so it's bullshit to probe for any properties of the circuit when grounding input
<DocScrutinizer05>
sorry I have to say that, but that except of the suggests the book is wrong regarding that. I can't rule out the rest of the book provides context that redefines the situation
<DocScrutinizer05>
so what? doesn't apply to circuits operated outside their operational range
<DocScrutinizer05>
"zero" means "with respect to the allowed input voltage swing, which is +/-x Volt around zero"
<DocScrutinizer05>
for your circuit 0 volt isn't the middle of the allowed voltage swing, it isn't even inside allowed voltage swing at all
<DocScrutinizer05>
somebody ommitted bias, as I said a dozen times already
<DocScrutinizer05>
that circuit is broken from oversimplification
<DocScrutinizer05>
depending on particular type of MOSFET used in input stage
<DocScrutinizer05>
the usual mosfet will close completely when gate is on source level
<DocScrutinizer05>
so that transistor isn't operating in its linear range which is a BAD THING for a linear amp
<DocScrutinizer05>
not in linear rnage means the transistor can't close even more when you apply a negative voltage with respect to GND to the input. Usually that is called CLIPPING
<DocScrutinizer05>
clipping is something you need to avoid by all means for a linear amp
<promach>
DocScrutinizer05: that test circuit is for small-signal analysis of Rout
<DocScrutinizer05>
WTF, you build a circuit that is made to test some property of that circuit? what's its true useage
<DocScrutinizer05>
small signal HAHA. There is no signal small enough to bring that test circuit in b) out of clipping
<DocScrutinizer05>
so forget it
<DocScrutinizer05>
tis IS NO amp
<DocScrutinizer05>
it starts to become an amp when you apply at least 0.7V bias with respect to GND
<promach>
this is small-signal analysis, not DC analysis
<DocScrutinizer05>
bullshit
<DocScrutinizer05>
google clipping
<DocScrutinizer05>
then google DC-bias maybe
<DocScrutinizer05>
my ass
<DocScrutinizer05>
what you get in fig b) is Rout of an amp **IN CLIPPING MODE**. Everybody can tell you an amp in clipping doesn'T work as amp anymore
<DocScrutinizer05>
it's saturated, clipping, outside of specs, not functional
<DocScrutinizer05>
not my fault you forgot DC-bias of input gate and DC-blocker capacitor
<DocScrutinizer05>
go test your thing in a simulator, you will notice it has a gain of -infinite
<DocScrutinizer05>
unless you apply a bia of at least 0.7 V (or whatever t´is that particular MOSFETs gate voltage where it starts to open D-S channel)
<promach>
I know you are concerned about DC analysis, but simulator also has AC analysis, right ?
<DocScrutinizer05>
ZERO means AC-zero, NOT DC-zero
<DocScrutinizer05>
NOOOO!
<promach>
it definitely has, otherwise, we will not have gain-phase plot
<promach>
bode plot
<DocScrutinizer05>
what the fuck is so hard to understand in "fig b) doesn't show an amp"?
<promach>
I understand that "fig b) doesn't show an amp"?
<DocScrutinizer05>
no fucking DC-analysis, ITS BROKEN BY DESIGN
<promach>
it is not meant for DC analysis
<DocScrutinizer05>
so why do you drive it DC then??????
<DocScrutinizer05>
tying gate to GND **IS DC**
<promach>
Vin is not driven by DC anymore
<promach>
after shorting to GND
<DocScrutinizer05>
apply two resistors for bias, and a DC-blocker capacitor and you are fine
* DocScrutinizer05
headdesks
<promach>
in AC analysis, DC bias is deemed GND
<DocScrutinizer05>
please take it elsewhere
<DocScrutinizer05>
your refusal to accept the simple fact that this circuit is broken by design starts to annoy
<promach>
it is broken in DC analysis
<promach>
not in AC analysis
<DocScrutinizer05>
initally you seem to have spotted the problem yourself when you asked why the feedback isn't working. It's not working BECAUSE the circuit is operated outside specs since it's missing bias and DC-blocking on input
<DocScrutinizer05>
fuck, you really are annoying
<DocScrutinizer05>
its broken. as linear amp. period.
<DocScrutinizer05>
no matter which analysis you run against it
<promach>
I just understand about AC analysis just now
<DocScrutinizer05>
do you understand about electronics too?
<DocScrutinizer05>
or _just_ about analysis
<DocScrutinizer05>
when this is about education at university then I have little hope for good circuits in the future
<DocScrutinizer05>
>>in AC analysis, DC bias is deemed GND<< yes, OUTSIDE your blackbox DUT
<DocScrutinizer05>
your blackbox however is missing INTERNAL bias
<DocScrutinizer05>
what makes you think your circuit can get away without the DC-blocker capacitor and internal input bias EVERY OTHER circuit has?
<qi-bot>
DocScrutinizer05 meant: "what makes you think your non-differential amp can get away without the DC-blocker capacitor and internal input bias EVERY OTHER non-differential amp has?"
<DocScrutinizer05>
>>For low distortion, the transistor must be biased so the output signal swing does not drive the transistor into a region of extremely nonlinear operation.<< tying gate to source puts the mosfet into a mode as extremely nonlinear as it gets: it's closed
<DocScrutinizer05>
>>the MOSFET must stay in the active mode (or saturation mode), and avoid cut-off or ohmic operation (or triode mode).<<
<DocScrutinizer05>
ETX, bye
<DocScrutinizer05>
listen buddy, when you're doing AC-analysis the you tie input to GND via a DC-blocker capacitor. You MUST NOT apply DC-bias in the form of tying input to GND with a wire
<DocScrutinizer05>
however you're doing exactly that and then you call it AC-analysis
<DocScrutinizer05>
get your educational books fixed!
<DocScrutinizer05>
when you actually do tie input to GND via a DC-blocker capacitor, you will notice your circuit is junk since it has no input bias circuit defining the operation point of the input stage transistor. The gate is floating