<azonenberg>
The final SMA match, in-line probe tip vs offset like i had before, then some tweaks to the tip geometry for fitting in tight spots better
<bvernoux>
ha very nice
<azonenberg>
Still have to do the new enclosure, i'm going to try moving to a one-piece design
<bvernoux>
it will be a flexpcb ?
<azonenberg>
No this one is rigid RO4350B, it's a competitor to the picoconnect probes
<azonenberg>
although much less expensive and with a form factor more like a standard scope probe
<bvernoux>
one small improvement could be to have via less far than the trace
<azonenberg>
Thats one of the things holding me back on the order - tweaking exact via spacing
<bvernoux>
recommended via spacing is 50mil
<azonenberg>
They're on a 1mm grid right now center to center so via-trace-via
<azonenberg>
edge of drill to edge of trace right now is 0.6 mm
<bvernoux>
with via drill 0.4064 mm & via size 0.762 mm
<azonenberg>
The vias are 0.5mm diameter with 0.3mm drills
<azonenberg>
1mm pitch
<bvernoux>
yes but recommended is 1.27mm 50mil ;)
<bvernoux>
I do not know what that change
<azonenberg>
Recommended where, for what geometry?
<bvernoux>
from manufacturer
<bvernoux>
up to 26.5GHz
<azonenberg>
what manufacturer?
<azonenberg>
and for microstrip or CPW?
<bvernoux>
CPW
<bvernoux>
pi-CCS-JOHN-142-0771-831.pdf
<bvernoux>
from BelFuse
<bvernoux>
For optimum high frequency circuit board performance, use the following fabrication guidelines:
<bvernoux>
Place 16 mil diameter ground vias on both sides of the coplanar waveguide line, spaced
<bvernoux>
at 50 mil intervals along the entire length of the line.
<bvernoux>
anyway you are not far and I do not know what that change exactly
<azonenberg>
Yeah. This is one of the things i want a higher edition of sonnet for
<bvernoux>
it is just recomended for their SMA endlaunch connectors
<azonenberg>
L2 Basic's RAM limit is problematic wrt simulating actual size/shape vias
<bvernoux>
ha you cannot simulate that ?
<azonenberg>
I modeled my via fence as a long box
<azonenberg>
Individual vias add a lot more polygons which needs more ram
<bvernoux>
ha yes I see
<azonenberg>
I can do it, but not for a substantial area
<azonenberg>
Especially if you model them as round vs square
<bvernoux>
I plan to use 142-0771-831 or 142-0761-891 for my future Test Boards
<bvernoux>
as they seems quite good and up to 26.5GHz
<azonenberg>
I'm using SMA-J-P-H-ST-EM1
<bvernoux>
but about 14USD per connector ...
<azonenberg>
for the time being
<bvernoux>
yes it is way cheaper about 4USD/unit
<bvernoux>
even less
<bvernoux>
I'm doing a new revision of your Test Probe ;)
<azonenberg>
oh?
<bvernoux>
using the optimal values for OSHPark 4 layers
<azonenberg>
oh you mean the microstrip with smas for testing probes on?
<bvernoux>
with cheap SMA like SMA-J-P-H-ST-EM1 and other compatible ...
<bvernoux>
CPW
<azonenberg>
yeah but i mean, a version of that
<bvernoux>
yes
<azonenberg>
If it turns out good send me the gerbers so i can have some made for here
<bvernoux>
my previous version was very strange and act like a low pass filter ;)
<azonenberg>
Lol
<azonenberg>
Yeah i did not characterize mine super well and it wasnt optimized with the field solver
<bvernoux>
so now I have used all perfect values for OSHPark 4 Layers ;)
<bvernoux>
trace 0.34mm
<bvernoux>
also I have found a very strange bug
<bvernoux>
as you connector was on the EdgeCuts
<bvernoux>
there was a short
<bvernoux>
in fact edge cuts was converted in Copper Layer on all layers
<bvernoux>
maybe it could explain my strange results too
<azonenberg>
edge cuts was put into copper?
<azonenberg>
that sounds like an export problem
<bvernoux>
a very good check for that is to use ZofzPCB with IPC-D-356Netlist
<azonenberg>
(i dont use kicad import for anything, i export gerbers and visually double check them before ordering)
<bvernoux>
it detecte things are shorted ...
<bvernoux>
yes edge cuts was put into different layers
<bvernoux>
you can say it shall be not a problem as it will be cut
<bvernoux>
but if the cut is not big it can keep some shorts
<bvernoux>
so a safe margin is to never have SMA connectors on border on the Edge Cut
<azonenberg>
i would say the proper thing to do is not export edge cuts onto other layers :)
<bvernoux>
on your SMA Probe I have just moved the SMA connector +0.3mm and all is ok
<bvernoux>
yes it seems clearly a bug with export in Kicad
<azonenberg>
There's a checkbox 'exclude pcb edge layer from other layers'
<azonenberg>
it's checked by default, which means you do not plot edge cuts on other copper
<bvernoux>
but that issue appears with 5.0.5-2 latest stable and also latets nightly build
<azonenberg>
if unchecked, edge cuts is plotted on copper
<bvernoux>
ha yes it is unchecked ;)
<azonenberg>
So that explains everything then
<bvernoux>
it was the mistake ;)
<azonenberg>
PEBKAC :)
<bvernoux>
what an awfull option
<bvernoux>
I have never checked that ;)
<azonenberg>
Yeah i've never looked at it either
<azonenberg>
its always been checked by default for me
<azonenberg>
i wonder if a recent change unchecked it
<azonenberg>
i'm on 5.1.4
<bvernoux>
hmm interesting
<bvernoux>
anyway it is safe to avoid have connector or other things on the border ;)