03:17 <mkk_> [Tim 'mithro' Ansell, skywater-pdk] I think @John McMaster was looking into doing some type of graphic to GDS renderer which which satisfied DRCs

03:29 <mkk_> [Tim 'mithro' Ansell, skywater-pdk] Just randomly came across https://research.google/pubs/pub47442/

03:29 <mkk_> [Tim 'mithro' Ansell, skywater-pdk] Experimental Analysis of a Ring Oscillator Network for Hardware Trojan Detection in a 90nm ASIC

03:46 <mkk_> [Kevin Baragona, skywater-pdk] On a related note, has anyone ever tried making a ring oscillator in Verilog or VHDL? I tried some years ago and it made the tooling surprisingly unhappy. I was then advised that such a design could actually damage an FPGA.

03:51 <mkk_> [Mehdi Saligane, skywater-pdk] I think it is feasible, and seen that before but I have never used to say it works!

04:34 <mkk_> [Tim 'mithro' Ansell, skywater-pdk] @Kevin Baragona Many people have but the tooling generally pretty unhappy with them

04:35 <mkk_> [Tim 'mithro' Ansell, skywater-pdk] @Kevin Baragona I would suggest #yosys and ##openfpga on http://irc.freenode.net are good place to ask about that type of thing

08:23 <mkk_> [FatsieFS, skywater-pdk] @Kevin Baragona Synthesis does not want logic loops in the design and timing can

08:24 <mkk_> [FatsieFS, skywater-pdk] ... They want signals going from register to register or IO and clocked. And a RO is basically a logical loop.

08:25 <mkk_> [FatsieFS, skywater-pdk] *timing can't handle it. (Seems I am not awake yet)

08:33 <mkk_> 1. you are likely to do custom instantiation of cells from a library of standard cells (or some primitives if you are using FPGA)

08:33 <mkk_> [Ronan BARZIC, skywater-pdk] @Kevin Baragona: yes it is doable, but

08:33 <mkk_> 2. you need to prevent the synthesis tool to keep those cells (a string a 3 inverters would be replaced by only only) using dont_touch or keep attribute depending of the synthesis tool

08:33 <mkk_> 3. you need to break the timing loop through some set_false_path (or equivalent command)

19:47 <mkk_> [Austin Rovinski, skywater-pdk] @Kevin Baragona See `bsg_clk_gen` as part of the `basejump_stl` library: https://github.com/bespoke-silicon-group/basejump_stl/tree/master/bsg_clk_gen. It is a parameterized free-running oscillator. Tested in silicon.

21:54 <mkk_> [Tim 'mithro' Ansell, skywater-pdk] @Adrian Freed The OSU cell library should have transmission gates