<mkk_>
[matt venn, skywater-pdk] I'm doing another interview, this time with @ about their PLL design. If you have any questions you'd like to ask, just DM me or put in a thread here.
<lkcl>
yes, a couple: first, how easy would it be to adapt to other geometries
<lkcl>
the second: are there any plans to add a built-in clock divider / generator
<lkcl>
so as to be able to do multiple clock frequencies for things like low-power mobile processors?
<lkcl>
that cannot be done externally because it messes with clock trees and timing.