<finn_>
that's the top, I have a wrapper test bench which at the moment just drives that input clock
<finn_>
created the PLL core with yosys pll tool
<finn_>
icepll -i 12 -o 60 -f pll.v -m
<finn_>
REFERENCECLK is driven correctly in the gtk
<finn_>
PLLOUTCORE is showing as undefined
<ZipCPU>
Yeah, ok, now I understand your problem.
<ZipCPU>
Typically what you'll want to do is to create a toplevel design and a main design below that.
<ZipCPU>
The toplevel design contains all the things, like the SB_PLL and the original clock, that cannot be simulated.
<ZipCPU>
The main design contains all the things you can simulate.
<ZipCPU>
You'll then create a wrapper around the main design, not the toplevel design.
<ZipCPU>
Your wrapper will then create both clocks.
<ZipCPU>
Sorry for my initial confusion--my background is signal processing, and I thought you wanted to synchronize to an incoming signal using your own version of a PLL.
<finn_>
So what you're saying is the tools will not simulate the PLL?
<ZipCPU>
I wouldn't expect them to. Tools that will simulate a PLL tend to cost much, much more. ;)
<finn_>
like modelsim?
<finn_>
well this is useful to know, I'll have to change my designs around a little bit
<ZipCPU>
Perhaps, but I don't know if modelsim will simulate *this* PLL on this chip.
<finn_>
in your experience, which is the best free verilog simulator ?
<ZipCPU>
Gosh ... funny you should ask ... I *love* Verilator.
<finn_>
trying to create a VGA adaptor which isn't going well
<qu1j0t3>
adapting what to what? I/m interested in vga signal generation when i eventually figure out how to program this DE0
<qu1j0t3>
(it's scarily old so i don't know how successful this will be in terms of tools)
<finn_>
At the moment I have a ice40-hx8k breakoutboard
<finn_>
I've wired the header pins to a PMOD VGA connector
* qu1j0t3
nods
<finn_>
and that pastebin above should draw me some boxes
<qu1j0t3>
this Terasic TREX C1 has VGA outgoing already
<finn_>
at the moment I get on my screen "unsupported format"
<qu1j0t3>
ha. :)
<qu1j0t3>
got a scope?
<finn_>
ugh no
<finn_>
well
<finn_>
kind of
<finn_>
someone at work gave me a logic analyser
<finn_>
but it's only 24Mhz
<finn_>
but I can at least see the signals are coming out of the pins
<finn_>
bit stuck so thought I'd roll back and start back in simulation
<ZipCPU>
Need a VGA logic simulator?
<awygle>
ZipCPU has quite a few good blog posts about getting information on what's going on inside your fpga
<qu1j0t3>
finn_: yeah, i guess that'd still be good for lower resolutions
<finn_>
Well I understand how VGA works so I don't need a simulator, I just need to understand why that above pastebin won't work aha
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<ZipCPU>
:LOL: Are you sure??
<ZipCPU>
Do you know what a VGA simulator might offer you?
<finn_>
what would it offer me
<finn_>
ok go for it
<ZipCPU>
So, I have a VGA simulator that checks the horizontal and vertical synch wires coming from your code, to make sure they match what they are supposed to be.
<finn_>
I'll have a look
<ZipCPU>
The pixels are also drawn into an X-Window (GTKMM) on your screen, so you can "see" the result your code would create.
<finn_>
ok then :)
<ZipCPU>
Hence, when you run your simulator within verilator, you can see the results of your code plotted on your screen.
<ZipCPU>
If things don't work, you've still got the VCD file so that you can trace *every* wire.
<ZipCPU>
Once you move to the actual FPGA, figuring out what the wires were doing along the way is ... more difficult/challenging.
<finn_>
So verilator is more about looking at the i/o of the module than individual wires?
<ZipCPU>
It is complete enough so that you can also simulate external component wires as well.
<ZipCPU>
One of the problems with an iverilog approach is that, while you can simulate your design, you make struggle to simulate how your design interacts with the rest of the world.
<ZipCPU>
Verilator offers you an easy C/C++ environment for creating that "rest of the world".
<ravenexp>
^^
<finn_>
I see
<ravenexp>
I used it to turn pin flipping back into UDP packets
<ZipCPU>
I tend to communicate with my designs over TCP/IP. I have software to turn TCP streams into either UART commands for an actual board, or simulated UART commands when running a Verilator based design.
<ravenexp>
I use 10BASE-T Ethernet instead of an UART
<ZipCPU>
Meh ... almost all of my designs have UART's, few of them have ethernet's. Of those that do, they don't have the same ethernet controller so ... that doesn't work very well for me.
<ravenexp>
my ethernet controller is a verilog core
<ravenexp>
I just pull it into the project
<ravenexp>
it only requires two IOs for RX and TX
<ravenexp>
that's why I went with 10M ethernet
<ZipCPU>
Makes sense.
<ravenexp>
100M would require a PHY
<ZipCPU>
All I've got are PHY's.
<ravenexp>
it's amazing how backwards compatible ethernet is
<ravenexp>
I can plug a 10M device into a gigabit switch and it just works
<ZipCPU>
Heheh ...
<ZipCPU>
Just like the space shuttle engines and milspecs ... ;)
<qu1j0t3>
as i understand it, that means the system was proved to be unsatisfiable.
<qu1j0t3>
the otehr possible outcome being satisfiable (SAT).
<promach>
how can UNSAT -> PASS on page 11 ?
<finn_>
Do you know off the top of your head what `timescale yosys library files use?
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<ZipCPU>
Is it relevant?
<ZipCPU>
You can declare another timescale, if you would rather.
<ZipCPU>
Remember .... only simulation depends upon the timescale. Nothing else does.
<finn_>
I'm getting these really long warnings
<finn_>
>> /usr/local/share/yosys/ice40/cells_sim.v:7: warning: timescale for SB_IO inherited from another file. infra/hdl/clks_sim.v:1: ...: The inherited timescale is here.
<ZipCPU>
Although, I'll admit that my tool is rather antiquated.
<cr1901_modern>
It looks like inkscape
<ZipCPU>
I need to learn inkscape. Inkscape has better support.
<awygle>
ZipCPU: do we need to assert the clock toggling? Seems like if we assert that the inputs only change on a toggle the solver should advance the clock for us
<ZipCPU>
Correct.
<ZipCPU>
I just can't stand reading a vcd file with no clock toggling.
<awygle>
Fair enough :-P. Although if my FIFO failed when the clock wasn't toggling I'd certainly want to know!
<ZipCPU>
If thee clocks not toggling, my FIFO has already failed.
<ZipCPU>
I shall humbly submit to your greatness, though, if you can get your FIFO to work with no clock.
<ZipCPU>
;P
* awygle
furiously googles "asynchronous fifo"
<cr1901_modern>
It's basically the only foolproof way to do clock domain crossings
<cr1901_modern>
incidentally, that EE times article that every references glosses over it
<cr1901_modern>
ZipCPU: I'm not sure I like the explanation of temportal induction. I'd rather say:
<cr1901_modern>
"The temporal induction step assumes that all assertions hold for each state in an arbitrary set of n - 1 state transitions.
<cr1901_modern>
It then proves that all asserts hold in _all_ nth states reachable from an arbitrary set of n - 1 state transitions."
<awygle>
I was hoping for some cool unclocked asynchronous fifo rather than just a cross clock domain fifo.
<awygle>
Didn't find anything though
<awygle>
Not sure FIFOs actually make sense in that paradigm
<cr1901_modern>
I mean, the Intel 8259 PIC doesn't have a clock, but it is most certainly a stateful chip
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<ZipCPU>
cr1901_modern ... I need to run, but ... is that really a better description of how induction works? I"m just quoting what I've heard so far ... hearing with little understanding.
<adityaP>
When I was testing my FIFO using yosys-SMTBMC, one thing which I found was the tool was incrementing the value of write pointer (output [5:0]wr_ptr) beyond it's permissible value ( in this case 32) and was generating counter example for it. We usually constrain the input in Formal verification. But I needed to constrain my output value of wr_ptr so that my check is passed. Is constraining the output correct thing?
<ZipCPU>
adityaP: Check my post at zipcpu.com. I discuss that. gtg tho