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<noname_Matt>
I have a question about the use of RAM in designs. I want to implement a very stripped down SoC on the HX8K, using ideally no external components (RAM chips, peripherals, ect.) beyond maybe an SPI flash chip, to mkae the design as easy to replicate by others as possible. However, since this could end up being a pretty big CPU core, I'm concerned about how much fabric will be left to implement the SoC's RAM. What kind of impact could implementing the C
<noname_Matt>
PU core have on the ability to use the on-chip RAM? Can some of it become inaccessible even if I'm not using it in the CPU design itself (simply because there isn't fabric available to connect/implement it)?
<noname_Matt>
"pretty big CPU core" => in relative terms anyway, given this isn't a big chip
<sorear>
FPGAs tend to be pretty overprovisioned on routing
<sorear>
it's not unheard of to successfully use 100% of the LUTs
<sorear>
i wouldn't worry immediately
<noname_Matt>
Is the RAM in an ICE40 connected in such a way that some of the fabric is either RAM, or logic, but not both? (forcing a choice between logic or RAM)
<sorear>
no.
<noname_Matt>
I have heard that using say, all of the ram on some FPGAs means cutting the number of LUTs in half.
<sorear>
bear in mind that the HX8K has *16 KB* of RAM
<noname_Matt>
So, a lot less than the amount of space devoted to LUTs?
<sorear>
you have 7680 LUTs, 7680 flip-flop bits connected to luts, and 131,072 bits of block RAM
<noname_Matt>
Ah, ok, I was under the impression the "RAM" consisted of the flip-flops attached the the LUTs
<sorear>
each purple block contains 8 LUTs and 8 FFs (each directly attached to one LUT)
<sorear>
each yellow block contains 2048 bits of 8T SRAM (they can only be used in pairs, a RAMT and a RAMB together give you a 256x16 block RAM)
<sorear>
most other FPGA lines have "distributed RAM" which uses the bits of the LUT itself; e.g. a Xilinx 6-input LUT can be used as a 64-bit memory
<sorear>
most FPGA lines have both distributed RAM and block RAM; ice40 has only block RAM
<noname_Matt>
Why are some cells shaded in that diagram?
<noname_Matt>
Are they just the same type as the other (clickable) ones?
<sorear>
yes
<noname_Matt>
Thanks. Another question I have: If at some point I decide I want to be more RAM-greedy, whats the best way to go about adding more (single-port) RAM? Would it be to add an SRAM chip? Or are big ones (10KB -1MB) expensive? Would DRAM and an internal DRAM controller be an easier way to get more memory for less cost/effort overall?
<sorear>
so, the ice40UP5K has 4x 64KB jumbo block rams (SPRAM)
<sorear>
i can't really advise on external memory selection, that's beyond my current level
<noname_Matt>
That's ok.
<noname_Matt>
That chip looks interesting...a decent number of LUTs, quite a bit of RAM, and a package that doesn't look like pure evil...
<sorear>
fewer LUTs, and also about half the speed of the hx8k
<noname_Matt>
What's it's speed? I haven't even gotten to the speed part yet. (the car has to have wheels first, so to speak)
<noname_Matt>
Hrm. Mouser says 48 MHz, but what is that measurement exactly?the maximum clock you can supply to the chip?
<sorear>
not sure
<lutsabound>
I run a ZipCPU on an hx8k at 50mhz
<lutsabound>
That's sort of the answer to a different question tho
<daveshah>
The UP5K tends to be two to three times slower than the hx8k
<daveshah>
But ultimately frequency depends on your design
<daveshah>
In particular how long the longest path between registers is
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<noname_Matt>
Is the ICESTORM flow deterministic, particularly ArachePNR's annealing? Does it accept seed values to any RNGs?
<sorear>
arachne-pnr has a seed command-line option
<noname_Matt>
ok, thanks
<daveshah>
And that is the only PRNG used - it should always behave the same with the same seed even across machines