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<mithro> Does anyone know how to use yosys+vivado together?
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<ZipCPU> mithro: As I recall, you need to use the yosys synth_xililnx command with the edif output
<ZipCPU> You can then ingest the edif output into Vivado
<ZipCPU> That said, I don't recall doing it
<mithro> Yeap, I'm trying now
<ZipCPU> As I recall, yosys doesn't yet have DSP support--something I depend upon.
<mithro> 48.21. Executing AST frontend in derive mode using pre-parsed AST for module `\mor1kx_cfgrs'.
<mithro> ERROR: Module `\FDPE' referenced in module `\top' in cell `\FDPE_11' is not part of the design.
<awygle> iirc there's a blackbox option that says "hey some stuff will fill in later"?
<ZipCPU> mithro: Is that a yosys error or a Vivado error? I'm guessing yosys
<mithro> Yosys, code works with ISE and Vivado....
<awygle> what command dies, read_verilog?
<mithro> awygle: Yeah - looks like it...
<mithro> awygle: Looks like I can remove "hierarchy -top top" maybe?
<mithro> That seems to have gotten a bit further.... now I get
<mithro> 48.4.21. Executing AST frontend in derive mode using pre-parsed AST for module `\mor1kx_cfgrs'.
<mithro> ERROR: Module `IOBUF' referenced in module `top' in cell `IOBUF_15' does not have a port named 'IO'.
<mithro> Looks like the IOBUF module at https://github.com/YosysHQ/yosys/blob/master/techlibs/xilinx/cells_xtra.v is wrong?
* awygle shrugs
<awygle> i have made the single contribution available to me, i wish you luck
<awygle> i agree IOBUF seems wrong
<mithro> Fixing that seems to make things get further
<mithro> Yosys completed and now Vivado failed!
<awygle> lol
<mithro> Now I have to figure out how clock constraints and yosys' edif output should work together....
<mithro> ERROR: [DRC PLIDC-10] IDELAYCTRL missing for IODELAYs: There are 16 IDELAY/ODELAY/IODELAY cells in the design which requires IDelayCtrl, but there is no IDelayCtrl cell
<mithro> Failed at place design...
<mithro> which is a lot further!
<awygle> idelayctrl important
<mithro> I'm guessing that the issue is caused by the earlier failures to apply XDC
<mithro> CRITICAL WARNING: [Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_nets eth_rx_clk]'. [/home/tansell/github/timvideos/HDMI2USB-litex-firmware/build/arty_net_or1k.linux/gateware/top.xdc:336] Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock
<mithro> was used to create the clock object before it is referenced.
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<mithro> digshadow: You know your vivado TCL API - how do I get vivado to print the net names that are actually available to the above? I'm assuming yosys has renamed something so it no longer matches?