clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach_> Does yosys support calling variables from modules from different hierarchy ? I think this is a feature provided by systemverilog "bind". Please correct me if I am wrong
<daveshah> promach_: that page refers to Yosys' Verific SystemVerilog support
<daveshah> I don't think this feature is supported in Yosys on its own
<promach_> daveshah: so, not supported in yosys-smtbmc ?
<daveshah> promach_: not supported in Yosys' own verilog frontend
<daveshah> smtbmc is part of the solver interface and irrelevant here
<daveshah> Indeed Yosys with Verific uses the same smtbmc
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<ZipCPU> Wow. Just made my third pull request to Yosys. Guess I never thought of myself as nearly that capable.
<maikmerten> congratulations!
<ZipCPU> It took a lot of searching through the spec. I feel like I just spent the last 6 hrs spec searching to get it right.
<maikmerten> at least there's a spec that one can spend 6 hrs with ;-)
<ZipCPU> Lol
<ZipCPU> It was the Sys Verilog spec, dated 2012
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