clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<adumont> @zipcpu Hi, I'm @adumont from twitter
<ZipCPU> Good morning/afternoon!
<ZipCPU> Can I ask how old your yosys build is?
<ZipCPU> Is it a recent build from github?
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<adumont> @zipcpu #facepalm! indeed I was not using the latest yosys build I was using 0.7+606.
<ZipCPU> Well, let's keep working together ... Go ahead and build and tell me what takes place next
<ZipCPU> Let's get you from here to success
<ZipCPU> Don't forget---you may want to switch mode from cover to prove, depending on what you want to do
<adumont> @zipcpu: using Yosys 0.8+36 (git sha1 719e2940) (I believe I built it last week), it doesn't complay anymore! :)
<ZipCPU> Can I tweet that in response? Let me look like the hero? :D
<adumont> @zipcpu: sure, you solved the issue :)
* ZipCPU smiles broadly!
<ZipCPU> Feel free to come back here if you have other questions!
<ZipCPU> It's just too difficult to have a conversation over Twitter
<adumont> @zipcpu: noted :). thanks, I'll follow the tutorial. I'm really eager to learn about Formal Verification.
<ZipCPU> There are other kind souls on this channel that may also be willing to help you out as well, should I not be available.
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<adamgreig> in nextpnr-ice40, using lvds inputs, is it expected that i have to specify the negative input pin number instead of the positive one?
<daveshah> It should behave the same as arachne-pnr
<adamgreig> should arachne-pnr behave the same as the lattice docs sort of vaguely suggest? :p
<adamgreig> I will try with arachne-pnr and compare
<adamgreig> the chipdb has z=0 for -ve and z=1 for +ve, and ice40's isValidBelForCell returns false if z!=0
<adamgreig> (if lvds is enabled)
<adamgreig> aha
<adamgreig> nextpnr error message: ERROR: Bel 'X0/Y20/io1' of type 'SB_IO' is not valid for cell 'SB_IO' of type 'SB_IO'
<daveshah> I am pretty sure what we do matches the hardware
<adamgreig> but, arachne-pnr error message: fatal error: pcf error: LVDS port `adc_ain' not a DPxxB input
<daveshah> The vendor tools might abstract that more
<adamgreig> that's fair, I was just expecting to specify the A pin from the app note on lvds, but the arachne-pnr error makes it very clear to use the B input
<adamgreig> thanks for the pointer :)
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<adumont> Hi guys, I'm wondering if anyone could help me fix this warning when I pass verilator:
<adumont> %Warning-WIDTH: ram.v:23: Logical Operator IF expects 1 bit on the If, but If's VARREF 'ROMFILE' generates 104 bits.
<adumont> code looks like this:
<adumont> parameter ROMFILE = "";
<adumont> if( ROMFILE ) $readmemh(ROMFILE, mem);
<adumont> I guess there's a better way to put it, but I have been unable to find how. (right now I put this /* verilator lint_off WIDTH */, but I feel it's not the right way)
<ZipCPU> Hello, adumont!
<ZipCPU> IIRC, I have an example of this that works
* ZipCPU rummages through his file system
<ZipCPU> I used a generate statement
<ZipCPU> generate if (ROMFILE == 0) initial $readmemh(ROMFILE, mem); endgenerate
<tpb> Title: icozip/memdev.v at master · ZipCPU/icozip · GitHub (at github.com)
<ZipCPU> That said, it builds -- I'm not sure if I've actually executed the $readmemh in that example to know that it works
<adumont> @zipcpu thanks, I'll try that
<adumont> @zipcpu: actually, simply putting ROMFILE != 0 did the trick and now verilator doesn't give that warning. cool :)
<adumont> @zipcpu: been scratching my head with your tutorial's lesson 3 :), on page 42 of the pdf, you run the sby -f ledwalker.sby and it fails (on your screenshot). In my case, with your example files, it doesn't , it passes
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<ZipCPU> Let me check
<adumont> @zipcpu: I get this: http://termbin.com/uu4r
<ZipCPU> Are you set for cover or prove mode?
<ZipCPU> (You were set for cover mode--without a cover() statement, your design will trivially pass cover())
<adumont> your ledwalker.sby says mode cover on the 2nd line
<adumont> I haven't modified that
<ZipCPU> Yes. Remember what that mode line does?
<ZipCPU> So, here's what you need to remember about the source files: they are meant for you to learn from. They aren't fully functional. The idea was to have you work with them to make them so.
<ZipCPU> ... and, hopefully by so doing, to encourage you to learn all the more.
<ZipCPU> Sounds like you've just learned something from the discussion ;)
<ZipCPU> If you go back to the lesson, there was a discussion regarding cover and what it did
<adumont> @zipcpu: ah indeed! I'll rewind a bit in the lesson
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