clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<kc5tja> So glad that I did the integration test with Verilator. Found a bug that Yosys didn't catch, because no property existed for it.
<kc5tja> Always good to double-check your assumptions!
<ZipCPU> Yep!
<ZipCPU> Especially the assumptions!
<kc5tja> Not the formal assumptions, but the assumptions of the developer. ;)
<ZipCPU> Oh. We don't talk about those ...
<ZipCPU> ;)
<kc5tja> OK, I'm feeling confident that I can synthesize this core. At long last.
<ZipCPU> Really?
<ZipCPU> Like, the CPU core?
<kc5tja> No, the SIA core.
<ZipCPU> Ok
<kc5tja> I haven't even started work on the CPU yet. :)
<ZipCPU> Can you interact with it, like over TCP/IP for example?
<ZipCPU> That might make it easier to run your CPU from within the simulator and to interact with it
<kc5tja> I was going to use a USB-to-serial cable to test it on the FPGA.
<ZipCPU> Well, okay, you can do that too ... until something goes wrong
<kc5tja> I was going to build a simple state-machine that just implemented a simple echo driver for the SIA.
<kc5tja> Oh, you're talking about debugging the CPU, not the SIA. I'm talking about testing the SIA in isolation.
<ZipCPU> Okay
<kc5tja> I *DO* need to build a serial-to-bus-master adapter of some kind though, since that'll not only work for debugging, but also will serve a critical role for implementing peripheral expansion.
<ZipCPU> Don't forget the problem of loading the CPU with some design or other
<kc5tja> What do you mean by loading the CPU?
<ZipCPU> Setting up the flash or other memory so that there's a program waiting for the CPU to run
<kc5tja> Oh yeah, the bootstrap binary is embedded in the same flash as the FPGA configuration bitstream.
<kc5tja> That code is actually already tested; the ROM adapter was my very first TileLink slave device, as you might recall. The SIA is my second.
<ZipCPU> I'm not so much worried about the ROM device, but rather the CPU's instructions
<kc5tja> That's a solved problem already; I've already written an assembler and toolchain which allowed me to implement Forth for the Kestrel-2DX and port it to a simple emulation of the Kestrel-3 -- it boots and runs in the software emulator.
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