clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<swetland> so poking through the source, it looks like yosys understands *some* systemverilog. is that documented somewhere?
<tpb> Title: yosys/README.md at master · YosysHQ/yosys · GitHub (at github.com)
<swetland> thanks!
<swetland> oh yay, interfaces.
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<cr1901_modern> Why does icetime take such a HUGE amount of memory now? I can't compile it on an ARM SBC with _two_ GBs of mem.
<cr1901_modern> And 1GB of swap
<cr1901_modern> guess that means nextpnr is also hopeless thanks to boost python being god awful w/ mem usage