<daveshah>
Don't expect them to make a big difference at the moment though
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<swetland>
they don't seem to. I'm seeing enormous timing differences between lattice and nextpnr (and the design is not huge -- like 30-40% of a UP5K). I'm wondering if my use of the PLL is confusing it and maybe it's not sending the clocks across the SB_GBs.
<swetland>
trying to figure out how to figure out which signals are using the global routing resources
<daveshah>
Global promotion is automatic and won't make too big a difference
<daveshah>
Normally the FOSS tools are 20-40% behind the vendor ones
<daveshah>
swetland: seems like this is a Yosys bug
<daveshah>
It hasn't inferred block ram somewhere and is using LUTs instead
<swetland>
ah suppose so, more synthesis issue
<swetland>
yeah definitely the case
<swetland>
early days full of adventure. I keep bouncing back and forth between poking at the foss stuff because its shiny and gritting my teeth and dealing with the vendor stuff because it (more or less) works reliably.
<swetland>
looks like both the cpu's register file and the display's pattern rom are not using BRAM w/ yosys
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<ZipCPU>
Yeah ... the register file was a challenge for me as well
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<cr1901_modern>
>Normally the FOSS tools are 20-40% behind the vendor ones
<cr1901_modern>
Huh, I thought for ice40 "no significant difference exists". Also, kinda surprised icecube didn't choke when inferring block RAM
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<daveshah>
I wonder if the problem here is due to initial statements
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<daveshah>
icecube ignores them in all cases as if you were doing asic synthesis
<daveshah>
Yosys follows them pedantically and won't infer BRAM if there is an initial statement on the output reg
<daveshah>
Because ice40 BRAMs don't have a guaranteed initial output value
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<swetland>
icecube2/synplify will infer a pair of SB_BRAM256x16 from this, yosys will not:
<swetland>
reg [15:0] R[0:15];
<swetland>
always @(posedge clk) begin
<swetland>
if (wreg)
<swetland>
R[wsel] <= wdata;
<swetland>
end
<swetland>
assign adata = R[asel];
<swetland>
assign bdata = R[bsel];
<daveshah>
swetland: That is not physically possible on the ice40
<daveshah>
There must be a register somewhere else in the design that icecube is folding in
<swetland>
ah that would explain why if I manually instantiate a pair of SB_BRAM256x16 I do not get a working design
<daveshah>
Yup
<daveshah>
If there is an initial value on those registers that are being folded in, that would be enough to stop Yosys inferring bram
<daveshah>
Yosys should fold in registers too even if not in the same module as the ram
<swetland>
probably self-inflicted. should fully debug this little cpu in simulation first. and actually should probably design the register file to be synchronous as that's how it's going to work on the fpga
<daveshah>
Of course almost any other commercially available fpga will map that file to distributed ram just fine
<daveshah>
This is something of an ice40 peculiarity
<swetland>
okay, so I'm not entirely crazy
<swetland>
last time I did a bunch of fpga work it was with artix7
<daveshah>
ZipCPU had the same problem
<ZipCPU>
;)
<daveshah>
It's also quite wasteful to map a 256 bit register file to a 4kbit BRAM. Distributed ram is a much more efficient solution
<daveshah>
A shame SiliconBlue didn't include it really
<ZipCPU>
But the design doesn't fit in the device if you put the register file into FF's
<daveshah>
In this case it does - its just much larger than it needs to be
<swetland>
I was toying with adding banked registers to my toy cpu
<swetland>
just because of that
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