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<Kitlith>
if you're using the synth_ice40 command of yosys, is there some way to pass -sv to do stuff with systemverilog? or is that automatically enabled or something?
<MoeIcenowy>
Kltllth: I think -sv is proceed at Verilog loading stage
<MoeIcenowy>
not related to synthesis
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<ZipCPU>
Kitlith: If you are using the Verific front end, "read -sv file.sv" will synthesize a SystemVerilog file
<ZipCPU>
Just like "read -vhdl file.vhd" will read and process a VHDL file. Both require the Verific front-end library, and so both require the commercial/licensed version of yosys
<daveshah>
read -sv will work without Verific too, that's the point of the new read command as opposed to the older Verific command
<daveshah>
Of course the subset of SV supported without Verific will be much smaller
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<Kitlith>
MoeIcenowy, i only asked because the commands i was seeing online never even seemed to use a read or read_verilog comand in addition to synth_ice40
<Kitlith>
not using verific because "call for pricing" is an automatic "it's too expensive for me" as an individual
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<ZipCPU>
Kitlith: You can both drive yosys from a command line and from a script. read_verilog or read are things you'll often see within the script, followed by one of the synth* commands
<ZipCPU>
You can also adjust parameters, macro defines, and more from with the script--things harder to do when calling the synth* command from the command line