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<kitten_nb_five>
Hello. I am having trouble understanding the output of nextpnr, specifically the "Max frequency". I have a PLL instanciated(?) in my design, if i just change the module name(!!) from "pll _pll(...)" to "pll pll(...)" (and the constraint to use the correct name) i am getting 8MHz more or less max frequency. Is this normal? Changing a name should not change anything?
<daveshah>
Yes, synthesis and place and route as they are implemented in Yosys and nextpnr are chaotic processes
<daveshah>
Particularly for small designs or designs with only a few critical paths, the heuristics can be quite unstable
<kitten_nb_five>
ok, thank you
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<Lofty>
daveshah: I think nextpnr has quite a lot more chaos than Yosys to be fair
<daveshah>
Small chaos in Yosys tends to cause big chaos in nextpnr
<daveshah>
(or equally ABC)
<kitten_nb_five>
"Everybody can handle order, but only a genius can master chaos" :-)
<kitten_nb_five>
and yes, it's weird. I am adding more code and fmax increases... Good for me...
<Lofty>
ABC is absolutely applied chaos theory
<Lofty>
But I mean
<Lofty>
Until Yosys gets lossless synthesis, we'll have to settle, I think
<Lofty>
... Considering the flexibility of RTLIL it might be feasible at the cost of memory
<Lofty>
In practice it's probably not worth it outside of like fine-grained synthesis
<Lofty>
[Lossless synthesis marks points that are known to be equivalent with "choice nodes", which means you can pick whichever option maps the best]