clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<sammylin> I'm going through ZipCPU's formal exercises (https://zipcpu.com/tutorial/formal.html), but instead of using verific to parse VHDL, I'm using GHDL.
<sammylin> Complains: SBY 20:32:04 [counter_vhd] base: counter_vhd.sv:59: ERROR: syntax error, unexpected TOK_ID
<sammylin> That line is : bind counter counter_vhd
<sammylin> #(.MAX_AMOUNT(MAX_AMOUNT)) copy (.*);
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<ZipCPU> sammylin: bind is a SV construct that to my knowledge is only implemented with the VERIFIC parser
<ZipCPU> Similarly, I'm not sure the open source parser supports the .* notation.
<sammylin> I was afraid of that answer :( Guess I won't be able to use your AXI formal specs with VHDL for now.
<ZipCPU> Checkout pepijn's work from about a year ago or so
<ZipCPU> He used formal with VHDL IIRC
<sammylin> I did, he uses PSL.
<ZipCPU> I'd be curious to know how he did it
<ZipCPU> He spoke at ORCONF to present his work, so that'd be a good place to start when looking for it
<ZipCPU> Ah, PSL. Okay
<ZipCPU> That'd be where I would start.
<ZipCPU> How about this ...
<ZipCPU> Can you submodule the VHDL portion?
<ZipCPU> You don't necessarily need bind if you can make the module to be verified a submodule of the Verilog module with the properties
<sammylin> I'm not familiar enough with Verilog to know.
<ZipCPU> You might need to pass enough data back and forth to make assertions about the three counters, but ... that might be enough to get you going
<sammylin> I'll give it a shot.
<ZipCPU> o/
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