clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach3> vup: I know, I mean yosys script that calls ISE bitstream generator
<promach3> now, I have the bitstream, how do I put the bitstream onto Spartan-6 without opening ISE software itself ?
<vup> how is the fpga connected?
<promach3> JTAG
<vup> is the JTAG adapter supported by openocd?, if yes maybe take a look at this: https://tomverbeure.github.io/2019/09/15/Loading-a-Spartan-6-bitstream-with-openocd.html ?
<tpb> Title: Loading a Xilinx Spartan 6 bitstream with OpenOCD | Electronics etc… (at tomverbeure.github.io)
<promach3> vup: I am using FT2232H
<vup> then that should probabl
<vup> y work
<promach3> thanks for pointing out OpenOCD, let me try installing the software later
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<promach3> vup: I tried the webpage instruction, but I got the following error
<vup> promach3: try a slower speed maybe? its not detecting any xilinx devices in the chain, maybe there are SI issues
<promach3> vup: now I have `Info : 111 5 core.c:1142 jtag_examine_chain_display(): JTAG tap: xc6s.tap tap/device found: 0x44002093 (mfg: 0x049 (Xilinx), part: 0x4002, ver: 0x4)`
<promach3> however, I still could not load the bitstream onto the FPGA using `sudo /usr/bin/openocd -d -f ./digilent-hs1.cfg -f /usr/share/openocd/scripts/cpld/xilinx-xc6s.cfg -c "transport select jtag" -c "adapter speed 1000 init; xc6s_program xc6s.tap; pld load 0 ./ddr3_memory_controller_par.bit ; exit"` Why ?
<vup> well you did not give any error message or anything, so no clue?
<promach3> vup: here you go the log
<vup> promach3: other than leaving out the duplicate `transport select jtag`, I see nothing wrong, are you sure it did not actually load the bitstream?
<promach3> let me continue the debugging work later after I have my food
<vup> promach3: I mean are you sure the ddr controller actually works? Maybe try a simple blinky on the other led first?
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<promach3> vup: just tested a LED, the openOCD does not put the bitstream yet
<promach3> D3 on R9
<promach3> * D3 on `BANK2_IO_R9`
<promach3> what is the purpose of using `telnet` in this case ?
<promach3> besides, lowering the frequency speed to 100 still resulted in detection of AMD device instead of Xilinx device
<vup> well without error messages, I don't really know what the problem could be, you could try xc3sprog...
<promach3> vup: here you go the error log
<promach3> I suppose https://github.com/matrix-io/xc3sprog does not have FULL support for Spartan-6 ?
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<vup> promach3: not sure what FULL support means, but it should be possible to program Spartan-6 with it
<promach3> vup: may I know the exact command-line syntax to program xc6slx16-3ftg256 ?
<vup> promach3: man xc3sprog...
<vup> but `xc3sprog -c ftdi` should show the fpga
<vup> `xc3sprog -c ftdi bitstream.bit` should program it
<promach3> vup: I got some strange IDCODE issue from xc3sprog , probably spartan-6 is not yet fully supported ?
<vup> promach3: I mean it says spartan-6 is supported: http://xc3sprog.sourceforge.net/hardware.php
<tpb> Title: xc3sprog - Supported hardware (at xc3sprog.sourceforge.net)
<vup> it seems to me that there are some connection / SI issues
<promach3> vup: solved the connection issue, but still could not load the bitstream onto Spartan-6
<vup> hmm a dna of 0xfeffffffffffffff seems pretty sketchy, maybe still connection issues?
<promach3> vup: after few more tries, `Device failed to configure, INSTRUCTION_CAPTURE is 0x11` disappears
<promach3> but the bitstream still won't load
<promach3> however, I still have `DNA is 0xfeffffffffffffff`
<vup> well are you sure the bitstream is correct? can you check the DONE pin?
<vup> also you can try the `-v` option to get more information
<vup> but it seems like it actually writes the bitstream
<vup> yeah that sounds like it is programming the bitstream. What does the DONE pin say? (Is it low or high?)
<promach3> D3 is still not turned OFF after the bitstream is loaded
<promach3> this pdf is the FPGA board schematics
<vup> and D2?
<promach3> vup: D2 is connected to `FPGA_DONE` signal
<promach3> that `FPGA_DONE` pin is not user pin though
<promach3> I could not allocate signal to use that pin though
<vup> Yes but is D2 on or off? Or rather does it change after programming?
<promach3> vup: **D2 stays ON all the time** , be it before or after programming
<promach3> let me state it again : I do not have control over `FPGA_DONE` pin , hence D2
<promach3> * let me state it again : I do not have direct control over `FPGA_DONE` pin , hence D2
<vup> Yes but FPGA_DONE is low when the fpga is not configured and high when it is
<promach3> vup: it seems that the manufacturer had burned a startup bitstream into the SPI flash
<promach3> but it seems that the newly loaded bitstream from xc3sprog did not overwrite the startup bitstream
<promach3> at least from my visual observation of the LED blinking activities
<promach3> let me check manufacturer documents again, I could not overwrite the startup bitstream
<vup> promach3: yes, you are programming over jtag, the bitstream loaded from the SPI flash, if you want to overwrite that, you need to overwrite the SPI flash content
<promach3> vup: why need to overwrite SPI flash content ? I just want to load and run a bitstream
<promach3> there is no need to mess with SSPI flash for now
<promach3> * there is no need to mess with SPI flash for now
<promach3> * vup: why need to overwrite SPI flash content ? I just want to load and run a bitstream using JTAG
<vup> sure, I thought you wanted to do that. Is there an example bitstream from the manufacturer? Try loading that with openocd or xc3sprog
<promach3> I have a feeling that the startup bitstream from the SPI flash takes higher priority that the JTAG
<vup> it does not
<vup> well
<vup> depends on how you do it
<vup> if program over JTAG and then power cycle of course the fpga load the bitstream from the SPI flash again
<promach3> vup: What is the purpose of `PROG_B` ?
<vup> but if power up the board and then program the fpga over JTAG it will have the bitstream loaded you programmed over JTAG (until you powercycle)
<promach3> to be exact, `PROGRAM_B_2`
<promach3> because when I pull `PROGRAM_B_2` to ground, the D2 signal is low for few seconds
<vup> promach3: ug380
<promach3> which means `PROGRAM_B_2` plays a role in bitstream loading
<vup> its a Active-lLow asynchronous full-chip reset
<promach3> ok
<promach3> vup: now, I am still stucked at getting bitstream programmed through JTAG
<vup> well is there a bitstream provided by the manufacturer you could test xc3sprog with?
<promach3> <vup "well is there a bitstream provid"> yes
<promach3> let me try the manufacturer bitstream
<promach3> vup: I have two manufacturer bitstream, but both did not do anything, it seems
<promach3> I mean the JTAG-programmed bitstream do not perform the function
<promach3> vup: let me get back on debugging on this tomorrow. it is a bit late here
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