<justchen1369>
why is the latest release a year old?
<Degi>
Hm, there seems to be about a release every year, though occasionally two years without one... If you want the newest features usually downloading the git repo and building it yourself is the best way
<justchen1369>
thanks
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<justchen1369>
how might I convert a verilog file into a json logical gate representation, using only AND, OR, and NOT?
<gatecat>
justchen1369: something like synth; abc -g AND,OR; write_json out.json
<gatecat>
(note that NOT is implicit in the list of gates passed to abc)
<justchen1369>
alright I'll try that, thanks!
<justchen1369>
seems to be spitting a bunch of debug info into the file
<gatecat>
you could try setattr -unset src * before write_json
<gatecat>
but otherwise, for the most part whatever is parsing the json should just ignore the attributes section, then it shouldn't matter anywau
<gatecat>
*anyway
<justchen1369>
in netnames, does "bits" correspond with each logic gate's "name"?