00:21 <cyrozap> Hey, pointfree, I know you have that visualization of the routing matrix, but have you figured out the register mappings yet? If so, I'd like to add the routing stuff to my bitstream parsing tool.

02:02 <pointfree> cyrozap: You can watch me manually replace o's with register (byte) numbers and bit numbers live right here if you refresh every few minutes: http://odroid.0xffffffff.in/~deploy/psoc-switching/HV-bits-and-regs.txt ...I'm saving to that file from my acme text editor to my odroid server over sshfs.

02:03 <jn__> acme as in plan9?

02:04 <pointfree> Yes

02:50 <cyrozap> pointfree: Oh, neat!

02:50 <pointfree> cyrozap: HVB register'bit mappings are now all done. Labeling HVA right now...

03:05 <cyrozap> pointfree: What's the address base for those register numbers?

03:14 <pointfree> cyrozap: Each UDB is associated with an HV_L and an HV_R. Here's a register map: http://odroid.0xffffffff.in/~deploy/psoc-switching/psoc5lp-registers.txt (search for HV). The DSI's handle routing for the outer two UDB rows. HV_L's and HV_R's are identical as far as I can tell.

03:14 <pointfree> UDB B's and UDB A's follow a checker pattern across the UDB array starting with B's in the top-left corner. UDB B's use HVB's and UDB A's use HVA's

03:15 <pointfree> cyrozap: You may have noticed you can count the HV registers in pretty much the same way you count the HS registers -- vertically. https://cdn.rawgit.com/wiki/azonenberg/openfpga/images/hs-regs.svg

03:17 <pointfree> Well, the HS's have 6 columns of bits while the HV's have 4 ...but similar idea.

03:20 <pointfree> The staggering of wires in the HV switching ascii diagram confused me at first until I started counting the bits and registers in the same way as in the HS.

03:23 <pointfree> As for the HC, it's just the same 24-by-16 tile flipped and mirrored 32 times per HC.

03:24 <pointfree> I should get around to writing down how each HC subtile is flipped and mirrored.

03:26 <pointfree> The HS, HV, and HC are each 4 subtiles high.

03:29 <pointfree> note to self: Add HS, VS, and PI tiles to http://odroid.0xffffffff.in/~deploy/psoc-switching/switching.html

03:42 <pointfree> cyrozap: Here's the mappings from the HC into the UDB's of any given UDB pair: http://odroid.0xffffffff.in/~deploy/psoc-switching/hc-to-udbs-mapping.txt That mapping is for the top left corner, but it's the same for all pairs.

03:46 <pointfree> v0 through v127 being the vertical wires out of the UDB into the HC (for outputs) or into the PI tiles then the UDB (for inputs).

03:53 <pointfree> DSI[0..15]_HC to ports and peripherals mappings are more heterogenous and I don't have all of those right now.